jp2.c

嵌入式开发板连接程序源码

  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RCDR, SDRAM_RCDR_VAL));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RCTR, SDRAM_RCTR_VAL));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_REFCTR, SDRAM_REFCTR_VAL));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_PTR, SDRAM_PTR_VAL));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RRDR, SDRAM_RRDR_VAL));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RIR, SDRAM_RIR_VAL));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x5e000000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x5e000000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x6e000000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x7e000033));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x7e000033));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_4, 0xc0bf0005));
  
  CHECK(dbg_wb_read32(MC_BASE_ADDR+MC_CCR_4, &insn));
  printf("expected %x, read %x\n", 0xc0bf0005, insn);

  // SRAM initialized to 0x40000000
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_1, SRAM_BASE & 0xffff0000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_1, ~(SRAM_SIZE - 1) & 0xffff0000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_1, 0xc020001f));
#endif

#if 1
#define CPU_OP_ADR  0
#define CPU_SEL_ADR 1

  /* unstall the or1200 in highland_sys */
  printf("Unstall or1k\n");
  CHECK(dbg_wb_write32(0xb8070000, 2));

  CHECK(dbg_cpu1_read_ctrl(0, &stalled));
  if (!(stalled & 0x1)) {
    printf("8051 should be stalled\n");   // check stall 8051
    exit(1);
  }

  printf("Stall or1k\n");
  CHECK(dbg_cpu0_write_ctrl(0, 0x01));         // stall or1k

  printf("SDRAM test: \n");
  CHECK(dbg_wb_write32(SDRAM_BASE+0x00, 0x12345678));
  CHECK(dbg_wb_read32(SDRAM_BASE+0x00, &insn));
  printf("expected %x, read %x\n", 0x12345678, insn);
  if (insn != 0x12345678) exit(1);
  
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0000, 0x11112222));
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
  printf("expected %x, read %x\n", 0x11112222, insn);
  if (insn != 0x11112222) exit(1);

  CHECK(dbg_wb_write32(SDRAM_BASE+0x0004, 0x33334444));
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0008, 0x55556666));
  CHECK(dbg_wb_write32(SDRAM_BASE+0x000c, 0x77778888));
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0010, 0x9999aaaa));
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0014, 0xbbbbcccc));
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0018, 0xddddeeee));
  CHECK(dbg_wb_write32(SDRAM_BASE+0x001c, 0xffff0000));
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0020, 0xdeadbeef));
  
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
  printf("expected %x, read %x\n", 0x11112222, insn);
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0004, &insn));
  printf("expected %x, read %x\n", 0x33334444, insn);
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0008, &insn));
  printf("expected %x, read %x\n", 0x55556666, insn);
  CHECK(dbg_wb_read32(SDRAM_BASE+0x000c, &insn));
  printf("expected %x, read %x\n", 0x77778888, insn);
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0010, &insn));
  printf("expected %x, read %x\n", 0x9999aaaa, insn);
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0014, &insn));
  printf("expected %x, read %x\n", 0xbbbbcccc, insn);
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0018, &insn));
  printf("expected %x, read %x\n", 0xddddeeee, insn);
  CHECK(dbg_wb_read32(SDRAM_BASE+0x001c, &insn));
  printf("expected %x, read %x\n", 0xffff0000, insn);
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0020, &insn));
  printf("expected %x, read %x\n", 0xdeadbeef, insn);
    
  if (insn != 0xdeadbeef) {
    printf("SDRAM test failed !!!\n");
    exit(1);
  }
    else
    printf("SDRAM test passed\n");

  printf("SRAM test: \n");
  CHECK(dbg_wb_write32(SRAM_BASE+0x0000, 0x11112222));
  CHECK(dbg_wb_write32(SRAM_BASE+0x0004, 0x33334444));
  CHECK(dbg_wb_write32(SRAM_BASE+0x0008, 0x55556666));
  CHECK(dbg_wb_write32(SRAM_BASE+0x000c, 0x77778888));
  CHECK(dbg_wb_write32(SRAM_BASE+0x0010, 0x9999aaaa));
  CHECK(dbg_wb_write32(SRAM_BASE+0x0014, 0xbbbbcccc));
  CHECK(dbg_wb_write32(SRAM_BASE+0x0018, 0xddddeeee));
  CHECK(dbg_wb_write32(SRAM_BASE+0x001c, 0xffff0000));
  CHECK(dbg_wb_write32(SRAM_BASE+0x0020, 0xdedababa));
  
  CHECK(dbg_wb_read32(SRAM_BASE+0x0000, &insn));
  printf("expected %x, read %x\n", 0x11112222, insn);
  CHECK(dbg_wb_read32(SRAM_BASE+0x0004, &insn));
  printf("expected %x, read %x\n", 0x33334444, insn);
  CHECK(dbg_wb_read32(SRAM_BASE+0x0008, &insn));
  printf("expected %x, read %x\n", 0x55556666, insn);
  CHECK(dbg_wb_read32(SRAM_BASE+0x000c, &insn));
  printf("expected %x, read %x\n", 0x77778888, insn);
  CHECK(dbg_wb_read32(SRAM_BASE+0x0010, &insn));
  printf("expected %x, read %x\n", 0x9999aaaa, insn);
  CHECK(dbg_wb_read32(SRAM_BASE+0x0014, &insn));
  printf("expected %x, read %x\n", 0xbbbbcccc, insn);
  CHECK(dbg_wb_read32(SRAM_BASE+0x0018, &insn));
  printf("expected %x, read %x\n", 0xddddeeee, insn);
  CHECK(dbg_wb_read32(SRAM_BASE+0x001c, &insn));
  printf("expected %x, read %x\n", 0xffff0000, insn);
  CHECK(dbg_wb_read32(SRAM_BASE+0x0020, &insn));
  printf("expected %x, read %x\n", 0xdedababa, insn);
 
  if (insn != 0xdedababa) {
    printf("SRAN test failed!!!\n");
    exit(1);
  }
    else
    printf("SRAM test passed\n");

  #if 1
    test_sdram();
  #endif

  CHECK(dbg_wb_write32(SDRAM_BASE+0x00, 0xe0000005));   /* l.xor   r0,r0,r0   */
  CHECK(dbg_wb_write32(SDRAM_BASE+0x04, 0x9c200000));   /* l.addi  r1,r0,0x0  */
  CHECK(dbg_wb_write32(SDRAM_BASE+0x08, 0x18400000));   /* l.movhi r2,0x4000  */
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0c, 0xa8420030));   /* l.ori   r2,r2,0x30 */
  CHECK(dbg_wb_write32(SDRAM_BASE+0x10, 0x9c210001));   /* l.addi  r1,r1,1    */
  CHECK(dbg_wb_write32(SDRAM_BASE+0x14, 0x9c210001));   /* l.addi  r1,r1,1    */
  CHECK(dbg_wb_write32(SDRAM_BASE+0x18, 0xd4020800));   /* l.sw    0(r2),r1   */
  CHECK(dbg_wb_write32(SDRAM_BASE+0x1c, 0x9c210001));   /* l.addi  r1,r1,1    */
  CHECK(dbg_wb_write32(SDRAM_BASE+0x20, 0x84620000));   /* l.lwz   r3,0(r2)   */
  CHECK(dbg_wb_write32(SDRAM_BASE+0x24, 0x03fffffb));   /* l.j     loop2      */
  CHECK(dbg_wb_write32(SDRAM_BASE+0x28, 0xe0211800));   /* l.add   r1,r1,r3   */

  CHECK(dbg_cpu0_write((0 << 11) + 17, 0x01));  /* Enable exceptions */
  CHECK(dbg_cpu0_write((6 << 11) + 20, 0x2000));  /* Trap causes stall */
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE));  /* Set PC */
  CHECK(dbg_cpu0_write((6 << 11) + 16, 1 << 22));  /* Set step bit */
  for(i = 0; i < 11; i++) {
    CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* 11x Unstall */
    do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
  }

  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000010, 0x00000028, 5);
  result = npc + ppc + r1;

  CHECK(dbg_cpu0_write((6 << 11) + 16, 0));  /* Reset step bit */
  CHECK(dbg_wb_read32(SDRAM_BASE + 0x28, &insn));  /* Set trap insn in delay slot */
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x28, 0x21000001));
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x28, insn));  /* Set back original insn */
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000010, 0x00000028, 8);
  result = npc + ppc + r1 + result;

  CHECK(dbg_wb_read32(SDRAM_BASE + 0x24, &insn));  /* Set trap insn in place of branch insn */
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x24, 0x21000001));
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x10));  /* Set PC */
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x24, insn));  /* Set back original insn */
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000028, 0x00000024, 11);
  result = npc + ppc + r1 + result;

  CHECK(dbg_wb_read32(SDRAM_BASE + 0x20, &insn));  /* Set trap insn before branch insn */
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, 0x21000001));
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x24));  /* Set PC */
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn));  /* Set back original insn */
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000024, 0x00000020, 24);
  result = npc + ppc + r1 + result;

  CHECK(dbg_wb_read32(SDRAM_BASE + 0x1c, &insn));  /* Set trap insn behind lsu insn */
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x1c, 0x21000001));
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x20));  /* Set PC */
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x1c, insn));  /* Set back original insn */
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000020, 0x0000001c, 49);
  result = npc + ppc + r1 + result;

  CHECK(dbg_wb_read32(SDRAM_BASE + 0x20, &insn));  /* Set trap insn very near previous one */
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, 0x21000001));
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x1c));  /* Set PC */
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn));  /* Set back original insn */
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000024, 0x00000020, 50);
  result = npc + ppc + r1 + result;

  CHECK(dbg_wb_read32(SDRAM_BASE + 0x10, &insn));  /* Set trap insn to the start */
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x10, 0x21000001));
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x20)  /* Set PC */);
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x10, insn));  /* Set back original insn */
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000014, 0x00000010, 99);
  result = npc + ppc + r1 + result;

  CHECK(dbg_cpu0_write((6 << 11) + 16, 1 << 22));  /* Set step bit */
  for(i = 0; i < 5; i++) {
    CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
    do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
  }
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000028, 0x00000024, 101);
  result = npc + ppc + r1 + result;

  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x24));  /* Set PC */
  for(i = 0; i < 2; i++) {
    CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
    do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
  }
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000010, 0x00000028, 201);
  result = npc + ppc + r1 + result;
  printf("result = %.8lx\n", result ^ 0xdeaddae1);


  { // 8051 TEST
    unsigned long npc[3], tmp;

    // WRITE ACC
    CHECK(dbg_cpu1_write(0x20e0, 0xa6));

    // READ ACC
    CHECK(dbg_cpu1_read(0x20e0, &tmp));   // select SFR space
    printf("Read  8051   ACC = %0x (expected a6)\n", tmp);
    result = result + tmp;

    // set exception to single step to jump over a loop
    CHECK(dbg_cpu1_write(0x3010, 0xa0)); // set single step and global enable in EER
    CHECK(dbg_cpu1_write(0x3011, 0x40)); // set evec = 24'h000040
    CHECK(dbg_cpu1_write(0x3012, 0x00)); // (already reset value)
    CHECK(dbg_cpu1_write(0x3013, 0x00)); // (already reset value)

    // set HW breakpoint at PC == 0x41
    CHECK(dbg_cpu1_write(0x3020, 0x41)); // DVR0 = 24'h000041
    CHECK(dbg_cpu1_write(0x3023, 0x39)); // DCR0 = valid, == PC
    CHECK(dbg_cpu1_write(0x3001, 0x04)); // DSR = watchpoint

    // flush 8051 instruction cache
    CHECK(dbg_cpu1_write(0x209f, 0x00));

    // Put some instructions in ram (8-bit mode on wishbone)
    CHECK(dbg_wb_write8 (0x40, 0x04));  // inc a
    CHECK(dbg_wb_write8 (0x41, 0x03));  // rr a;
    CHECK(dbg_wb_write8 (0x42, 0x14));  // dec a; 
    CHECK(dbg_wb_write8 (0x43, 0xf5));  // mov 0e5h, a;
    CHECK(dbg_wb_write8 (0x44, 0xe5));

    // unstall just 8051
    CHECK(dbg_cpu1_write_reg(0, 0));

    // read PC
    CHECK(dbg_cpu1_read(0, &npc[0]));
    CHECK(dbg_cpu1_read(1, &npc[1]));
    CHECK(dbg_cpu1_read(2, &npc[2]));
    printf("Read  8051   npc = %02x%02x%02x (expected 41)\n", npc[2], npc[1], npc[0]);
    result = result + (npc[2] << 16) + (npc[1] << 8) + npc[0];

    // READ ACC
    CHECK(dbg_cpu1_read(0x20e0, &tmp));   // select SFR space
    printf("Read  8051   ACC = %0x (expected a7)\n", tmp);
    result = result + tmp;

    // set sigle step to stop execution
    CHECK(dbg_cpu1_write(0x3001, 0x20)); // set single step and global enable in DSR

    // clear DRR
    CHECK(dbg_cpu1_write(0x3000, 0x00)); // set single step and global enable in DRR

    // unstall just 8051
    CHECK(dbg_cpu1_write_reg(0, 0));

    // read PC
    CHECK(dbg_cpu1_read(0, &npc[0]));
    CHECK(dbg_cpu1_read(1, &npc[1]));
    CHECK(dbg_cpu1_read(2, &npc[2]));
    printf("Read  8051   npc = %02x%02x%02x (expected 42)\n", npc[2], npc[1], npc[0]);
    result = result + (npc[2] << 16) + (npc[1] << 8) + npc[0];

    // READ ACC
    CHECK(dbg_cpu1_read(0x20e0, &tmp));   // select SFR space
    printf("Read  8051   ACC = %0x (expected d3)\n", tmp);
    result = result + tmp;

    printf("report (%x)\n", result ^ 0x6c1 ^ 0xdeaddead);
  }
#endif
}

int main(int argc,  char *argv[]) {
  char *redirstr;
  int trace_fd = 0;
  char *s;
  int err = DBG_ERR_OK;

  int c;
  const char *args;
  char *port;
  char *cable;

  srand(getpid());
  if ((argc < 3) || (argv[1][0] == '-') || (argv[2][0] == '-')) {
    printf("JTAG protocol via parallel port for linux.\n");
    printf("Copyright (C) 2001 Marko Mlinar, [e-mail]\n\n");
    printf("Usage: %s [cable] [JTAG port_number]\n", argv[0]);
    jp_print_cable_help();
    return -1;
  }

  cable = argv[1];
  port = argv[2];

  if (!jp_select_cable(cable)) {
    fprintf(stderr,"Error selecting cable %s\n", cable);
    return -1;
  }

  /* Get the cable-arguments */
  args = jp_get_cable_args();

  /* Parse the cable arguments (if-any) */
  for(;;) {
    c = getopt(argc, argv, args);
    if(c == -1)
      break;
    if(c == '?')
      return 1;
    if(!jp_cable_opt(c, optarg))
      return 1;
  }
  if(!jp_init_cable())
    return 1;

  /* Initialize a new connection to the or1k board, and make sure we are
     really connected.  */
  current_chain = -1;
  if ((err = dbg_reset())) goto error;

  /* Test the connection.  */
  dbg_test();
    
  /* We have a connection.  Establish server.  */
  serverPort = strtol(port,&s,10);
  if(*s) return -1;

  if(server_fd = GetServerSocket("or1ksim","tcp", serverPort)) {
    printf("JTAG Proxy server started on port %d\n", serverPort);
    printf("Press CTRL+c to exit.\n");
  } else {
    fprintf(stderr,"Cannot start JTAG Proxy server on port %d\n", serverPort);
    exit(-1);
  }
  
  /* Do endless loop of checking and handle GDB requests.  Ctrl-c exits.  */
  HandleServerSocket(true);
  return 0;
error:
  fprintf(stderr,"Connection with jtag via parallel port failed (err = %d).\n", err);
  exit(-1);
}