jp2.c

嵌入式开发板连接程序源码

  if (crc_read != crc_generated) {
    if (retry_do()) goto try_again;
    else return DBG_ERR_CRC;
  }
  /* we should read expected status value, otherwise retry */
  if (status != 0) {
    if (retry_do()) goto try_again;
    else return status;
  }
  jp2_write_JTAG(TMS); /* UPDATE_DR */
  jp2_write_JTAG(0); /* IDLE */  

  /* reset retry counter */
  retry_ok();
  return DBG_ERR_OK;
}
/* issues a burst read/write */
int dbg_go(unsigned char *data, unsigned short len, int read) {
  int status, crc_generated, crc_read;
  int i;

try_again:
  dbg_set_chain(dbg_chain);
  debug("\n");
  debug2("go len = %d\n", len);

  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
  jp2_write_JTAG(0); /* CAPTURE_DR */
  jp2_write_JTAG(0); /* SHIFT_DR */      
  
  /* write data, EXIT1_DR */
  crc_w = 0xffffffff;
  jp2_write_stream(DI_GO | (0<<DC_SIZE), DC_SIZE + 1, 0);
  if (!read) {
    /* reverse byte ordering, since we must send in big endian */
    for (i = 0; i < len; i++)
      jp2_write_stream(data[i], 8, 0);
  }
  jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
  crc_r = 0xffffffff;
  if (read) {
    /* reverse byte ordering, since we must send in big endian */
    for (i = 0; i < len; i++)
      data[i] = jp2_read_stream(data[i], 8, 0);
  }
  status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
  crc_generated = crc_r;
  crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
  
  /* CRCs must match, otherwise retry */
  //printf("%x %x %x\n", status, crc_read, crc_generated);
  if (crc_read != crc_generated) {
    if (retry_do()) goto try_again;
    else return DBG_ERR_CRC;
  }
  /* we should read expected status value, otherwise retry */
  if (status != 0) {
    if (retry_do()) goto try_again;
    else return status;
  }
  jp2_write_JTAG(TMS); /* UPDATE_DR */
  jp2_write_JTAG(0); /* IDLE */  

  /* reset retry counter */
  retry_ok();
  return DBG_ERR_OK;
}

/* read a word from wishbone */
int dbg_wb_read32(unsigned long adr, unsigned long *data) {
  int err;
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
  if ((err = dbg_command(0x6, adr, 4))) return err;
  if ((err = dbg_go((unsigned char*)data, 4, 1))) return err;
  *data = ntohl(*data);
  return err;
}

/* write a word to wishbone */
int dbg_wb_write32(unsigned long adr, unsigned long data) {
  int err;
  data = ntohl(data);
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
  if ((err = dbg_command(0x2, adr, 4))) return err;
  if ((err = dbg_go((unsigned char*)&data, 4, 0))) return err;
  return DBG_ERR_OK;
}

/* write a word to wishbone */
int dbg_wb_write16(unsigned long adr, unsigned short data) {
  int err;
  data = ntohs(data);
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
  if ((err = dbg_command(0x1, adr, 2))) return err;
  if ((err = dbg_go((unsigned char*)&data, 2, 0))) return err;
  return DBG_ERR_OK;
}

/* write a word to wishbone */
int dbg_wb_write8(unsigned long adr, unsigned long data) {
  int err;
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
  if ((err = dbg_command(0x0, adr, 1))) return err;
  if ((err = dbg_go((unsigned char*)&data, 1, 0))) return err;
  return DBG_ERR_OK;
}

/* read a block from wishbone */
int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len) {
  int i, err;
  //printf("%08x %08x\n", adr, len);
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
  if ((err = dbg_command(0x6, adr, len))) return err;
  if ((err = dbg_go((unsigned char*)data, len, 1))) return err;
  for (i = 0; i < len / 4; i ++) data[i] = ntohl(data[i]);
  //printf("%08x\n", err);
  return DBG_ERR_OK;
}

/* read a block from wishbone */
int dbg_wb_read_block16(unsigned long adr, unsigned short *data, int len) {
  int i, err;
  //printf("%08x %08x\n", adr, len);
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
  if ((err = dbg_command(0x5, adr, len))) return err;
  if ((err = dbg_go((unsigned char*)data, len, 1))) return err;
  for (i = 0; i < len / 2; i ++) data[i] = ntohs(data[i]);
  //printf("%08x\n", err);
  return DBG_ERR_OK;
}

/* read a block from wishbone */
int dbg_wb_read_block8(unsigned long adr, unsigned char *data, int len) {
  int i, err;
  //printf("%08x %08x\n", adr, len);
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
  if ((err = dbg_command(0x4, adr, len))) return err;
  if ((err = dbg_go((unsigned char*)data, len, 1))) return err;
  //printf("%08x\n", err);
  return DBG_ERR_OK;
}

/* write a block to wishbone */
int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len) {
  int i, err;
  for (i = 0; i < len / 4; i ++) data[i] = ntohl(data[i]);
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
  if ((err = dbg_command(0x2, adr, len))) return err;
  if ((err = dbg_go((unsigned char*)data, len, 0))) return err;
  return DBG_ERR_OK;
}

/* write a block to wishbone */
int dbg_wb_write_block16(unsigned long adr, unsigned short *data, int len) {
  int i, err;
  for (i = 0; i < len / 2; i ++) data[i] = ntohs(data[i]);
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
  if ((err = dbg_command(0x1, adr, len))) return err;
  if ((err = dbg_go((unsigned char*)data, len, 0))) return err;
  return DBG_ERR_OK;
}

/* write a block to wishbone */
int dbg_wb_write_block8(unsigned long adr, unsigned char *data, int len) {
  int i, err;
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
  if ((err = dbg_command(0x0, adr, len))) return err;
  if ((err = dbg_go((unsigned char*)data, len, 0))) return err;
  return DBG_ERR_OK;
}

/* read a register from cpu */
int dbg_cpu0_read(unsigned long adr, unsigned long *data) {
  int err;
  if ((err = dbg_set_chain(DC_CPU0))) return err;
  if ((err = dbg_command(0x6, adr, 4))) return err;
  if ((err = dbg_go((unsigned char*)data, 4, 1))) return err;
  *data = ntohl(*data);
  return DBG_ERR_OK;
}

/* write a cpu register */
int dbg_cpu0_write(unsigned long adr, unsigned long data) {
  int err;
  data = ntohl(data);
  if ((err = dbg_set_chain(DC_CPU0))) return err;
  if ((err = dbg_command(0x2, adr, 4))) return err;
  if ((err = dbg_go((unsigned char*)&data, 4, 0))) return err;
  return DBG_ERR_OK;
}

/* read a register from cpu */
int dbg_cpu1_read(unsigned long adr, unsigned long *data) {
  int err;
  if ((err = dbg_set_chain(DC_CPU1))) return err;
  if ((err = dbg_command(0x6, adr, 4))) return err;
  if ((err = dbg_go((unsigned char*)data, 4, 1))) return err;
  *data = ntohl(*data);
  return DBG_ERR_OK;
}

/* write a cpu register */
int dbg_cpu1_write(unsigned long adr, unsigned long data) {
  int err;
  data = ntohl(data);
  if ((err = dbg_set_chain(DC_CPU1))) return err;
  if ((err = dbg_command(0x2, adr, 4))) return err;
  if ((err = dbg_go((unsigned char*)&data, 4, 0))) return err;
  return DBG_ERR_OK;
}

/* write a cpu module register */
int dbg_cpu1_write_reg(unsigned long adr, unsigned char data) {
  int err;
  if ((err = dbg_set_chain(DC_CPU1))) return err;
  if ((err = dbg_ctrl(data & 2, data &1))) return err;
  return DBG_ERR_OK;
}

/* read a register from cpu module */
int dbg_cpu1_read_ctrl(unsigned long adr, unsigned char *data) {
  int err;
  int r, s;
  if ((err = dbg_set_chain(DC_CPU1))) return err;
  if ((err = dbg_ctrl_read(&r, &s))) return err;
  *data = (r << 1) | s;
  return DBG_ERR_OK;
}

/* write a cpu module register */
int dbg_cpu0_write_ctrl(unsigned long adr, unsigned char data) {
  int err;
  if ((err = dbg_set_chain(DC_CPU0))) return err;
  if ((err = dbg_ctrl(data & 2, data &1))) return err;
  return DBG_ERR_OK;
}

/* read a register from cpu module */
int dbg_cpu0_read_ctrl(unsigned long adr, unsigned char *data) {
  int err;
  int r, s;
  if ((err = dbg_set_chain(DC_CPU0))) return err;
  if ((err = dbg_ctrl_read(&r, &s))) return err;
  *data = (r << 1) | s;
  return DBG_ERR_OK;
}

void check(char *fn, int l, int i) {
  if (i != DBG_ERR_OK) {
    fprintf(stderr, "%s:%d: Jtag error %d occured; exiting.\n", fn, l, i);
    exit(1);
  }
}


void test_sdram (void) {
  unsigned long insn;
  unsigned long i;
  unsigned long data4_out[0x08];
  unsigned long data4_in[0x08];
  unsigned short data2_out[0x10];
  unsigned short data2_in[0x10];
  unsigned char data1_out[0x20];
  unsigned char data1_in[0x20];
          
  printf("Start SDRAM WR\n");
  for (i=0x10; i<(SDRAM_SIZE+SDRAM_BASE); i=i<<1) {
    //printf("0x%x: 0x%x\n", SDRAM_BASE+i, i);
    CHECK(dbg_wb_write32(SDRAM_BASE+i, i));
  }
  
  printf("Start SDRAM RD\n");
  for (i=0x10; i<(SDRAM_SIZE+SDRAM_BASE); i=i<<1) {
    CHECK(dbg_wb_read32(SDRAM_BASE+i, &insn));
    //printf("0x%x: 0x%x\n", SDRAM_BASE+i, insn);
    if (i != insn) {
      printf("SDRAM not OK");
      exit (1);
    }
  }

  printf("32-bit block write from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
  for (i=0; i<(0x20/4); i++) {
    data4_out[i] = data4_in[i] = ((4*i+3)<<24) | ((4*i+2)<<16) | ((4*i+1)<<8) | (4*i);
    //printf("data_out = %0x\n", data4_out[i]);
  }
    
  //printf("Press a key for write\n"); getchar();
  CHECK(dbg_wb_write_block32(SDRAM_BASE, &data4_out[0], 0x20));

  // 32-bit block read is used for checking
  printf("32-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
  CHECK(dbg_wb_read_block32(SDRAM_BASE, &data4_out[0], 0x20));
  for (i=0; i<(0x20/4); i++) {
    //printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
    if (data4_in[i] != data4_out[i]) {
      printf("SDRAM data differs. Expected: 0x%0x, read: 0x%0x\n", data4_in[i], data4_out[i]);
      exit(1);
    }
  }

  printf("16-bit block write from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
  for (i=0; i<(0x20/2); i++) {
    data2_out[i] = data2_in[i] = ((4*i+1)<<8) | (4*i);
    //printf("data_out = %0x\n", data_out[i]);
  }
  CHECK(dbg_wb_write_block16(SDRAM_BASE, &data2_out[0], 0x20));

  // 16-bit block read is used for checking
  printf("16-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
  CHECK(dbg_wb_read_block16(SDRAM_BASE, &data2_out[0], 0x20));
  for (i=0; i<(0x20/2); i++) {
    //printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
    if (data2_in[i] != data2_out[i]) {
      printf("SDRAM data differs. Expected: 0x%0x, read: 0x%0x\n", data2_in[i], data2_out[i]);
      exit(1);
    }
  }

  printf("8-bit block write from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
  for (i=0; i<(0x20/1); i++) {
    data1_out[i] = data1_in[i] = (4*i);
    //printf("data_out = %0x\n", data_out[i]);
  }
  CHECK(dbg_wb_write_block8(SDRAM_BASE, &data1_out[0], 0x20));

  // 32-bit block read is used for checking
  printf("8-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
  CHECK(dbg_wb_read_block8(SDRAM_BASE, &data1_out[0], 0x20));
  for (i=0; i<(0x20/1); i++) {
    //printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
    if (data1_in[i] != data1_out[i]) {
      printf("SDRAM data differs. Expected: 0x%0x, read: 0x%0x\n", data1_in[i], data1_out[i]);
      exit(1);
    }
  }
}


void dbg_test() {
  int i;
  unsigned long npc, ppc, r1, insn, result;
  unsigned char stalled;
#if 1
#define MC_BASE_ADDR     0x93000000
#define FLASH_BASE_ADDR  0xf0000000
#define FLASH_BAR_VAL    FLASH_BASE_ADDR
#define FLASH_AMR_VAL    0xf0000000
#define FLASH_WTR_VAL    0x00011009
#define FLASH_RTR_VAL    0x01002009
#define SDRAM_BASE_ADDR  0x00000000
#define SDRAM_BAR_VAL    SDRAM_BASE_ADDR
//#define SDRAM_SIZE       0x04000000  defined at the start of this program
#define SDRAM_AMR_VAL    (~(SDRAM_SIZE -1))
#define SDRAM_RATR_VAL   0x00000006
#define SDRAM_RCDR_VAL   0x00000002
#define SDRAM_RCTR_VAL   0x00000006
#define SDRAM_REFCTR_VAL 0x00000006
#define SDRAM_PTR_VAL    0x00000001
#define SDRAM_RRDR_VAL   0x00000000
#define SDRAM_RIR_VAL    0x000000C0

#define MC_BAR_0         0x00
#define MC_AMR_0         0x04
#define MC_WTR_0         0x30
#define MC_RTR_0         0x34
#define MC_OSR           0xe8
#define MC_BAR_1         0x08
#define MC_BAR_4         0x80
#define MC_AMR_1         0x0c
#define MC_AMR_4         0x84
#define MC_CCR_1         0x24
#define MC_CCR_4         0xa0
#define MC_RATR          0xb0
#define MC_RCDR          0xc8
#define MC_RCTR          0xb4
#define MC_REFCTR        0xc4
#define MC_PTR           0xbc
#define MC_RRDR          0xb8
#define MC_RIR           0xcc
#define MC_ORR           0xe4
        
  //usleep(1000000);

  printf("Stall 8051\n");
  CHECK(dbg_cpu1_write_reg(0, 0x01)); // stall 8051

  printf("Stall or1k\n");
  CHECK(dbg_cpu0_write_ctrl(0, 0x01));      // stall or1k

  CHECK(dbg_cpu1_read_ctrl(0, &stalled));
  if (!(stalled & 0x1)) {
    printf("8051 should be stalled\n");   // check stall 8051
    exit(1);
  }

  CHECK(dbg_cpu0_read_ctrl(0, &stalled));
  if (!(stalled & 0x1)) {
    printf("or1k should be stalled\n");   // check stall or1k
    exit(1);
  }

  printf("Initialize Memory Controller\n");
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_0, FLASH_BAR_VAL & 0xffff0000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_0, FLASH_AMR_VAL & 0xffff0000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_WTR_0, FLASH_WTR_VAL));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RTR_0, FLASH_RTR_VAL));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x40000000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_4, SDRAM_BAR_VAL & 0xffff0000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_4, SDRAM_AMR_VAL & 0xffff0000));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_4, 0x00bf0005));
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RATR, SDRAM_RATR_VAL));