oplogic.cpp

来自「motorola ezx 平台下的fba模拟器」· C++ 代码 · 共 673 行 · 第 1/2 页

  if (cc!=1 && ea<8) ot("  sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);
  ot("\n");

  EaCalc (0,0x003f, ea,size);
  EaWrite(0,     1, ea,size,0x003f);

  OpEnd();
  return 0;
}

// Emit a Asr/Lsr/Roxr/Ror opcode
static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
{
  char pct[8]=""; // count
  int shift=32-(8<<size);

  if (count>=1) sprintf(pct,"#%d",count); // Fixed count

  if (usereg)
  {
    ot(";@ Use Dn for count:\n");
    ot("  and r2,r8,#7<<9\n");
    ot("  ldr r2,[r7,r2,lsr #7]\n");
    ot("  and r2,r2,#63\n");
    ot("\n");
    strcpy(pct,"r2");
  }
  else if (count<0)
  {
    ot("  mov r2,r8,lsr #9 ;@ Get 'n'\n");
    ot("  and r2,r2,#7\n\n"); strcpy(pct,"r2");
  }

  // Take 2*n cycles:
  if (count<0) ot("  sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");
  else Cycles+=count<<1;

  if (type<2)
  {
    // Asr/Lsr
    if (dir==0 && size<2)
    {
      ot(";@ For shift right, use loworder bits for the operation:\n");
      ot("  mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));
      ot("\n");
    }

    if (type==0 && dir) ot("  mov r3,r0 ;@ save old value for V flag calculation\n");

    ot(";@ Shift register:\n");
    if (type==0) ot("  movs r0,r0,%s %s\n",dir?"asl":"asr",pct);
    if (type==1) ot("  movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);

    if (dir==0 && size<2)
    {
      ot(";@ restore after right shift:\n");
      ot("  mov r0,r0,lsl #%d\n",32-(8<<size));
      ot("\n");
    }

    OpGetFlags(0,0);
    if (usereg) { // store X only if count is not 0
      ot("  cmp %s,#0 ;@ shifting by 0?\n",pct);
      ot("  biceq r9,r9,#0x20000000 ;@ if so, clear carry\n");
      ot("  movne r1,r9,lsr #28\n");
      ot("  strneb r1,[r7,#0x45] ;@ else Save X bit\n");
    } else {
      // count will never be 0 if we use immediate
      ot("  mov r1,r9,lsr #28\n");
      ot("  strb r1,[r7,#0x45] ;@ Save X bit\n");
    }

    if (type==0 && dir) {
      ot(";@ calculate V flag (set if sign bit changes at anytime):\n");
      ot("  mov r1,#0x80000000\n");
      ot("  ands r3,r3,r1,asr %s\n", pct);
      ot("  cmpne r3,r1,asr %s\n", pct);
      ot("  biceq r9,r9,#0x10000000\n");
      ot("  orrne r9,r9,#0x10000000\n");
    }

    ot("\n");
  }

  // --------------------------------------
  if (type==2)
  {
    int wide=8<<size;

    // Roxr
    if(count == 1) {
      if(dir==0) {
        if(size!=2) {
		  ot("  orr r0,r0,r0,lsr #%i\n", size?16:24);
		  ot("  bic r0,r0,#0x%x\n", 1<<(32-wide));
		}
        GetXBit(0);
        ot("  movs r0,r0,rrx\n");
        OpGetFlags(0,1);
      } else {
        ot("  ldrb r3,[r7,#0x45]\n");
        ot("  movs r0,r0,lsl #1\n");
        OpGetFlags(0,1);
        ot("  tst r3,#2\n");
        ot("  orrne r0,r0,#0x%x\n", 1<<(32-wide));
        ot("  bicne r9,r9,#0x40000000 ;@ clear Z in case it got there\n");
      }
      ot("  bic r9,r9,#0x10000000 ;@ make suve V is clear\n");
      return 0;
    }

    if (usereg)
    {
      ot(";@ Reduce r2 until <0:\n");
      ot("Reduce_%.4x%s\n",op,ms?"":":");
      ot("  subs r2,r2,#%d\n",wide+1);
      ot("  bpl Reduce_%.4x\n",op);
      ot("  adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);
      ot("  beq norotx%.4x\n",op);
      ot("\n");
    }

    if (usereg||count < 0)
    {
      if (dir) ot("  rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);
    }
    else
    {
      if (dir) ot("  mov r2,#%d ;@ Reversed\n",wide+1-count);
      else     ot("  mov r2,#%d\n",count);
    }

    if (shift) ot("  mov r0,r0,lsr #%d ;@ Shift down\n",shift);

    ot(";@ Rotate bits:\n");
    ot("  mov r3,r0,lsr r2 ;@ Get right part\n");
    ot("  rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);
    ot("  movs r0,r0,lsl r2 ;@ Get left part\n");
    ot("  orr r0,r3,r0 ;@ r0=Rotated value\n");

    ot(";@ Insert X bit into r2-1:\n");
    ot("  ldrb r3,[r7,#0x45]\n");
    ot("  sub r2,r2,#1\n");
    ot("  and r3,r3,#2\n");
    ot("  mov r3,r3,lsr #1\n");
    ot("  orr r0,r0,r3,lsl r2\n");
    ot("\n");

    if (shift) ot("  movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);
    OpGetFlags(0,!usereg);
    if (!shift) {
      ot("  tst r0,r0\n");
      ot("  bicne r9,r9,#0x40000000 ;@ make sure we didn't mess Z\n");
    }
    if (usereg) { // store X only if count is not 0
      ot("  mov r2,r9,lsr #28\n");
      ot("  strb r2,[r7,#0x45] ;@ if not 0, Save X bit\n");
      ot("  b nozerox%.4x\n",op);
      ot("norotx%.4x%s\n",op,ms?"":":");
      ot("  adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
      OpGetFlags(0,0);
      ot("  ldrb r2,[r7,#0x45] ;@ C = old_X\n");
      ot("  and r2,r2,#2\n");
      ot("  orr r9,r9,r2,lsl #28\n");
      ot("nozerox%.4x%s\n",op,ms?"":":");
    }

    ot("\n");
  }

  // --------------------------------------
  if (type==3)
  {
    // Ror
    if (size<2)
    {
      ot(";@ Mirror value in whole 32 bits:\n");
      if (size<=0) ot("  orr r0,r0,r0,lsr #8\n");
      if (size<=1) ot("  orr r0,r0,r0,lsr #16\n");
      ot("\n");
    }

    ot(";@ Rotate register:\n");
    if (count<0)
    {
      if (dir) ot("  rsbs %s,%s,#32\n",pct,pct);
      ot("  movs r0,r0,ror %s\n",pct);
    }
    else
    {
      int ror=count;
      if (dir) ror=32-ror;
      if (ror&31) ot("  movs r0,r0,ror #%d\n",ror);
    }

    OpGetFlags(0,0);
    if (!dir) ot("  bic r9,r9,#0x10000000 ;@ make suve V is clear\n");
    if (dir)
    {
      ot(";@ Get carry bit from bit 0:\n");
      if (usereg)
      {
        ot("  cmp %s,#32 ;@ rotating by 0?\n",pct);
        ot("  tstne r0,#1 ;@ no, check bit 0\n");
      }
      else
        ot("  tst r0,#1\n");
      ot("  orrne r9,r9,#0x20000000\n");
      ot("  biceq r9,r9,#0x20000000\n");
    }
    else if (usereg)
    {
      // if we rotate something by 0, ARM doesn't clear C
      // so we need to detect that
      ot("  cmp %s,#0\n",pct);
      ot("  biceq r9,r9,#0x20000000\n");
    }
    ot("\n");

  }
  // --------------------------------------
  
  return 0;
}

// Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn
// (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)
int OpAsr(int op)
{
  int ea=0,use=0;
  int count=0,dir=0;
  int size=0,usereg=0,type=0;

  ea=0;
  count =(op>>9)&7;
  dir   =(op>>8)&1;
  size  =(op>>6)&3;
  if (size>=3) return 1; // use OpAsrEa()
  usereg=(op>>5)&1;
  type  =(op>>3)&3;

  if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8

  // Use the same opcode for target registers:
  use=op&~0x0007;

  // As long as count is not 8, use the same opcode for all shift counts::
  if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }
  if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn

  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler

  OpStart(op); Cycles=size<2?6:8;

  EaCalc(10,0x0007, ea,size,1);
  EaRead(10,     0, ea,size,0x0007,1);

  EmitAsr(op,type,dir,count, size,usereg);

  EaWrite(10,    0, ea,size,0x0007,1);

  OpEnd();

  return 0;
}

// Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee 
int OpAsrEa(int op)
{
  int use=0,type=0,dir=0,ea=0,size=1;

  type=(op>>9)&3;
  dir =(op>>8)&1;
  ea  = op&0x3f;

  if (ea<0x10) return 1;
  // See if we can do this opcode:
  if (EaCanRead(ea,0)==0) return 1;
  if (EaCanWrite(ea)==0) return 1;

  use=OpBase(op);
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler

  OpStart(op); Cycles=6; // EmitAsr() will add 2

  EaCalc (10,0x003f,ea,size,1);
  EaRead (10,     0,ea,size,0x003f,1);

  EmitAsr(op,type,dir,1,size,0);

  EaWrite(10,     0,ea,size,0x003f,1);

  OpEnd();
  return 0;
}

int OpTas(int op)
{
  int ea=0;
  int use=0;

  ea=op&0x003f;

  // See if we can do this opcode:
  if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;

  use=OpBase(op);
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler

  OpStart(op); Cycles=4;
  if(ea>=8) Cycles+=10;

  EaCalc (10,0x003f,ea,0,1);
  EaRead (10,     1,ea,0,0x003f,1);

  ot("  adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
  OpGetFlags(0,0);
  ot("\n");

#if CYCLONE_FOR_GENESIS
  // the original Sega hardware ignores write-back phase (to memory only)
  if (ea < 0x10) {
#endif
    ot("  orr r1,r1,#0x80000000 ;@ set bit7\n");

    EaWrite(10,     1,ea,0,0x003f,1);
#if CYCLONE_FOR_GENESIS
  }
#endif

  OpEnd();
  return 0;
}