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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"><html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1"><title>Sensorless control of 3-phase brushless DC motors: BLDC.h File Reference</title><link href="doxygen.css" rel="stylesheet" type="text/css"></head><body><!-- Generated by Doxygen 1.4.4 --><div class="qindex"><a class="qindex" href="main.html">Main Page</a> | <a class="qindex" href="files.html">File List</a> | <a class="qindex" href="globals.html">Globals</a></div><h1>BLDC.h File Reference</h1><hr><a name="_details"></a><h2>Detailed Description</h2>Atmel Corporation<p><ul><li>File : <a class="el" href="BLDC_8h.html">BLDC.h</a></li><li>Compiler : IAR EWAAVR 2.28a/3.10c</li></ul><p><ul><li>Support mail : <a href="mailto:avr@atmel.com">avr@atmel.com</a></li></ul><p><ul><li>Supported devices : ATmega48/88/168</li></ul><p><ul><li>AppNote : AVR444 - Sensorless control of three-phase brushless ' DC motors with ATmega48.</li></ul><p><ul><li>Description : Example of how to use the ATmega48 for sensorless control of a three phase brushless DC motor.</li></ul><p><dl compact><dt><b>Revision</b></dt><dd>1.1 </dd></dl><dl compact><dt><b>Date</b></dt><dd>Monday, October 10, 2005 11:15:46 UTC </dd></dl><p>Definition in file <a class="el" href="BLDC_8h-source.html">BLDC.h</a>.<p><p>This graph shows which files directly or indirectly include this file:<p><center><img src="BLDC_8h__dep__incl.png" border="0" usemap="#BLDC.hdep_map" alt=""></center><map name="BLDC.hdep_map"><area href="main_8c.html" shape="rect" coords="126,7,187,33" alt=""></map><p><a href="BLDC_8h-source.html">Go to the source code of this file.</a><table border="0" cellpadding="0" cellspacing="0"><tr><td></td></tr><tr><td colspan="2"><br><h2>Defines</h2></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a34">ADC_MUX_CURRENT</a> 0x3</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC multiplexer selection for current sampling. <a href="#a34"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a35">ADC_MUX_REF_VOLTAGE</a> 0x5</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC multiplexer selection for reference voltage sampling. <a href="#a35"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a33">ADC_MUX_SPEED_REF</a> 0x4</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC multiplexer selection for speed reference sampling. <a href="#a33"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a30">ADC_MUX_U</a> 0x0</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC multiplexer selection for channel U sampling. <a href="#a30"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a31">ADC_MUX_V</a> 0x1</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC multiplexer selection for channel V sampling. <a href="#a31"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a32">ADC_MUX_W</a> 0x2</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC multiplexer selection for channel W sampling. <a href="#a32"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a49">ADC_PRESCALER</a> ADC_PRESCALER_8</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC prescaler used. <a href="#a49"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a48">ADC_PRESCALER_16</a> ((1 << ADPS2) | (0 << ADPS1) | (0 << ADPS0))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC clock prescaled by 8 value. <a href="#a48"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a47">ADC_PRESCALER_8</a> ((0 << ADPS2) | (1 << ADPS1) | (1 << ADPS0))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC clock prescaled by 8 value. <a href="#a47"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a36">ADC_REF_CHANNEL</a> ((0 << REFS1) | (0 << REFS0))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC reference channel selection. <a href="#a36"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a37">ADC_RES_ALIGNMENT_BEMF</a> (1 << ADLAR)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC result alignment for BEMF measurement. <a href="#a37"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a39">ADC_RES_ALIGNMENT_CURRENT</a> (1 << ADLAR)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC result alignment for CURRENT measurement. <a href="#a39"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a40">ADC_RES_ALIGNMENT_REF_VOLTAGE</a> (1 << ADLAR)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC result alignment for reference voltage measurement. <a href="#a40"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a38">ADC_RES_ALIGNMENT_SPEED_REF</a> (1 << ADLAR)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC result alignment for speed reference measurement. <a href="#a38"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a66">ADC_RESOLUTION</a> 256</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">The ADC resolution used. <a href="#a66"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a50">ADC_TRIGGER_SOURCE</a> ((1 << ADTS2) | (0 << ADTS1) | (0 << ADTS0))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADC trigger source. <a href="#a50"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a78">ADC_ZC_THRESHOLD</a> 0x98</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Zero-cross threshold. <a href="#a78"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a45">ADMUX_CURRENT</a> (ADC_REF_CHANNEL | ADC_RES_ALIGNMENT_CURRENT | ADC_MUX_CURRENT)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADMUX register value for current sampling. <a href="#a45"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a46">ADMUX_REF_VOLTAGE</a> (ADC_REF_CHANNEL | ADC_RES_ALIGNMENT_REF_VOLTAGE | ADC_MUX_REF_VOLTAGE)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADMUX register value for reference voltage sampling. <a href="#a46"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a44">ADMUX_SPEED_REF</a> (ADC_REF_CHANNEL | ADC_RES_ALIGNMENT_SPEED_REF | ADC_MUX_SPEED_REF)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADMUX register value for speed reference sampling. <a href="#a44"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a41">ADMUX_U</a> (ADC_REF_CHANNEL | ADC_RES_ALIGNMENT_BEMF | ADC_MUX_U)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADMUX register value for channel U sampling. <a href="#a41"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a42">ADMUX_V</a> (ADC_REF_CHANNEL | ADC_RES_ALIGNMENT_BEMF | ADC_MUX_V)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADMUX register value for channel V sampling. <a href="#a42"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a43">ADMUX_W</a> (ADC_REF_CHANNEL | ADC_RES_ALIGNMENT_BEMF | ADC_MUX_W)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">ADMUX register value for channel W sampling. <a href="#a43"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a74">ANALOG_COMPARATOR_ENABLE</a></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a12">CCW</a> 1</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Counterclockwise rotation flag. Used only in macros. <a href="#a12"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a57">CLEAR_ALL_TIMER0_INT_FLAGS</a> (TIFR0 = TIFR0)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Macro that clears all Timer/counter0 interrupt flags. <a href="#a57"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a60">CLEAR_ALL_TIMER1_INT_FLAGS</a> (TIFR1 = TIFR1)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Macro that clears all Timer/Counter1 interrupt flags. <a href="#a60"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a79">COMMUTATION_CORRECTION</a> 50</td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a69">COMMUTATION_TIMING_IIR_COEFF_A</a> 1</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Input value relative gain in IIR filter. <a href="#a69"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a70">COMMUTATION_TIMING_IIR_COEFF_B</a> 3</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Relative feedback gain in IIR filter. <a href="#a70"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a73">CURRENT_LIMITER_CRITICAL</a> 3000</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">The current value in milliAmpere where the motor should be shut down. <a href="#a73"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a75">CURRENT_LIMITER_FACTOR</a> (1 / 5)</td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a72">CURRENT_LIMITER_START</a> 2500</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">The current value in milliAmpere where the current limiter starts to kick in. <a href="#a72"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a11">CW</a> 0</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Clockwise rotation flag. Used only in macros. <a href="#a11"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a13">DIRECTION_OF_ROTATION</a> CCW</td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a58">DISABLE_ALL_TIMER0_INTS</a> (TIMSK0 = 0)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Macro that disables all Timer/Counter0 interrupts. <a href="#a58"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a61">DISABLE_ALL_TIMER1_INTS</a> (TIMSK1 = 0)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Macro that disables all Timer/Counter1 interrupts. <a href="#a61"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a76">DISABLE_DRIVING</a> (DRIVE_PORT = 0x00)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Macro that cuts all power to the motor. <a href="#a76"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a29">DRIVE_DDR</a> DDRB</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Data direction register for drive pattern output. <a href="#a29"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a14">DRIVE_PATTERN_STEP1_CCW</a> ((1 << UL) | (1 << VH))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Drive pattern for commutation step 1, CCW rotation. <a href="#a14"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a20">DRIVE_PATTERN_STEP1_CW</a> ((1 << VH) | (1 << WL))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Drive pattern for commutation step 1, CW rotation. <a href="#a20"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a15">DRIVE_PATTERN_STEP2_CCW</a> ((1 << UL) | (1 << WH))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Drive pattern for commutation step 2, CCW rotation. <a href="#a15"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a21">DRIVE_PATTERN_STEP2_CW</a> ((1 << UH) | (1 << WL))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Drive pattern for commutation step 2, CW rotation. <a href="#a21"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a16">DRIVE_PATTERN_STEP3_CCW</a> ((1 << VL) | (1 << WH))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Drive pattern for commutation step 3, CCW rotation. <a href="#a16"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a22">DRIVE_PATTERN_STEP3_CW</a> ((1 << UH) | (1 << VL))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Drive pattern for commutation step 3, CW rotation. <a href="#a22"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a17">DRIVE_PATTERN_STEP4_CCW</a> ((1 << VL) | (1 << UH))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Drive pattern for commutation step 4, CCW rotation. <a href="#a17"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a23">DRIVE_PATTERN_STEP4_CW</a> ((1 << WH) | (1 << VL))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Drive pattern for commutation step 4, CW rotation. <a href="#a23"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a18">DRIVE_PATTERN_STEP5_CCW</a> ((1 << WL) | (1 << UH))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Drive pattern for commutation step 5, CCW rotation. <a href="#a18"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a24">DRIVE_PATTERN_STEP5_CW</a> ((1 << WH) | (1 << UL))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Drive pattern for commutation step 5, CW rotation. <a href="#a24"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a19">DRIVE_PATTERN_STEP6_CCW</a> ((1 << WL) | (1 << VH))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Drive pattern for commutation step 6, CCW rotation. <a href="#a19"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a25">DRIVE_PATTERN_STEP6_CW</a> ((1 << VH) | (1 << UL))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Drive pattern for commutation step 6, CW rotation. <a href="#a25"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a28">DRIVE_PORT</a> PORTB</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">PORT register for drive pattern output. <a href="#a28"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a26">EDGE_FALLING</a> 1</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Zero crossing polarity flag value for falling zero crossing. <a href="#a26"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a27">EDGE_RISING</a> 0</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Zero crossing polarity flag value for rinsing zero crossing. <a href="#a27"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a64">EXTERNAL_REF_VOLTAGE</a> ((4930UL * 10) / 43)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">External reference voltage in milliVolts. <a href="#a64"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a3">FALSE</a> 0</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Boolean FALSE value. <a href="#a3"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a81">MAX_PWM_COMPARE_VALUE</a> 200</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">The maximum allowed PWM compare value. <a href="#a81"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a54">MAX_RESTART_ATTEMPTS</a> 10</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">The maximum number of restart attempts without external action when stall is detected. <a href="#a54"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a83">MAX_SPEED</a> 8000UL</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">The maximum allowed speed. (Only has effect when closed loop speed control is used). <a href="#a83"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a80">MIN_PWM_COMPARE_VALUE</a> 90</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">The minimum allowed PWM compare value. <a href="#a80"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a82">MIN_SPEED</a> 3000UL</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">The minimum allowed speed. (Only has effect when closed loop speed control is used). <a href="#a82"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a84">P_REG_K_P</a> 64</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">P-regulator proportional gain. <a href="#a84"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a85">P_REG_SCALING</a> 65536</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">P-regulator scaling factor. The result is divided by this number. <a href="#a85"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a1">PWM_BASE_FREQUENCY</a> 20000</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">PWM base frequency. Used to calculate PWM TOP value. <a href="#a1"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a2">PWM_TOP_VALUE</a> (SYSTEM_FREQUENCY / PWM_BASE_FREQUENCY / 2)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">PWM TOP value. Automatically calculated to give desired <a class="el" href="BLDC_8h.html#a1">PWM_BASE_FREQUENCY</a>. <a href="#a2"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a56">SET_PWM_COMPARE_VALUE</a>(compareValue) (OCR0B = compareValue)</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Macro that sets a new duty cycle by changing the PWM compare value. <a href="#a56"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a59">SET_TIMER0_INT_ZC_DETECTION</a> (TIMSK0 = (1 << TOIE0))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Macro that enables Timer/Counter0 interrupt where zero crossings are detected. <a href="#a59"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a62">SET_TIMER1_INT_COMMUTATION</a> (TIMSK1 = (1 << OCIE1A))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Macro that enable Timer/Counter1 interrupt responsible for commutation. <a href="#a62"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a63">SET_TIMER1_INT_HOLDOFF</a> (TIMSK1 = (1 << OCIE1B))</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Macro that enables Timer/Counter1 interrupt responsible for enabling ADC sampling after ADC holdoff period. <a href="#a63"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a65">SHUNT_RESISTANCE</a> 220</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Current measurement shunt value in milliOhm. <a href="#a65"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a71">SPEED_CONTROL_OPEN_LOOP</a></td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Uncomment one of the following lines to choose open or closed loop speed control. <a href="#a71"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a52">STARTUP_DELAY_MULTIPLIER</a> 100</td></tr><tr><td class="mdescLeft"> </td><td class="mdescRight">Startup delays are given in milliseconds times STARTUP_DELAY_MULTIPLIER. <a href="#a52"></a><br></td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a53">STARTUP_LOCK_DELAY</a> 10000</td></tr><tr><td class="memItemLeft" nowrap align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="BLDC_8h.html#a51">STARTUP_NUM_COMMUTATIONS</a> 8</td></tr>⌨️ 快捷键说明
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