extra.c

系统启动时检测内存状况的软件C代码

	case 5: ddr = 2; break;
	case 6: ddr = 1; i852 = 1; break;
	default: ddr = 1;
	}

	if (ddr == 1)
	{
		cprint(POP_Y+3, POP_X+8, "tCAS:  ");
		cprint(POP_Y+5, POP_X+8, "(1) CAS 2.5 ");
		cprint(POP_Y+6, POP_X+8, "(2) CAS 2   ");
		if(!i852) {
			cprint(POP_Y+7, POP_X+8, "(3) CAS 3   ");
		}
		cas = getval(POP_Y+3, POP_X+15, 0);
	}
	else if (ddr == 2)
	{
		cprint(POP_Y+3, POP_X+8, "tCAS:  ");
		cprint(POP_Y+5, POP_X+8, "(1) CAS 4 ");
		cprint(POP_Y+6, POP_X+8, "(2) CAS 3 ");
		cprint(POP_Y+7, POP_X+8, "(3) CAS 5 ");
		cas = getval(POP_Y+3, POP_X+15, 0);
	}
	else
	{
		cas = -1;
	}

	popclear();
	return (cas);
}

void disclaimer(void)
{
	if ((ctrl == -1) || ( ctrl > sizeof(mem_ctr)/sizeof(mem_ctr[0])))
	{
		popclear();
		wait_keyup();
		cprint(POP_Y+3, POP_X+4, "   Chipset     ");
		cprint(POP_Y+4, POP_X+4, "Not supported !");
		get_key();
		wait_keyup();
		popclear();
	}
	else if (claim == 0)
	{
		ulong j = 0;

		while (j<500000)
		{
			cprint(POP_Y+1, POP_X+3, "Disclaimer : ");
			cprint(POP_Y+3, POP_X+3, "Modifying timing may ");
			cprint(POP_Y+4, POP_X+3, "cause system instability");
			cprint(POP_Y+5, POP_X+3, "proceed at your own risk");
			j++;
		}
		claim = 1;
		popclear();
	}
}

/////////////////////////////////////////////////////////
// here we go for the exciting timing change part...   //
/////////////////////////////////////////////////////////

void change_timing_i852(int cas, int rcd, int rp, int ras) {

	ulong dramtlr;
	ulong int1, int2;

	pci_conf_read(0, 0, 1, 0x60, 4, &dramtlr);

	// CAS Latency (tCAS)
	int1 = dramtlr & 0xFF9F;
	if      (cas == 2) { int2 = int1 ^ 0x20; }
	else if (cas == 1) { int2 = int1; }
	else		   { int2 = dramtlr; }


	// RAS-To-CAS (tRCD)
	int1 = int2 & 0xFFF3;
	if      (rcd == 2) { int2 = int1 ^ 0x8; }
	else if (rcd == 3) { int2 = int1 ^ 0x4; }
	else if (rcd == 4) { int2 = int1; }
	// else		   { int2 = int2; }


	// RAS Precharge (tRP)
	int1 = int2 & 0xFFFC;
	if      (rp == 2) { int2 = int1 ^ 0x2; }
	else if (rp == 3) { int2 = int1 ^ 0x1; }
	else if (rp == 4) { int2 = int1; }
	// else		  { int2 = int2; }


	// RAS Active to precharge (tRAS)
	int1 = int2 & 0xF9FF;
	if      (ras == 5)  { int2 = int1 ^ 0x0600; }
	else if (ras == 6)  { int2 = int1 ^ 0x0400; }
	else if (ras == 7)  { int2 = int1 ^ 0x0200; }
	else if (ras == 8)  { int2 = int1; }
	// else		    { int2 = int2; }

	pci_conf_write(0, 0, 1, 0x60, 4, int2);
	__delay(500);
}

void change_timing_i925(int cas, int rcd, int rp, int ras)
{
	ulong int1, dev0, temp;
	long *ptr;

	//read MMRBAR
	pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
	dev0 &= 0xFFFFC000;

	ptr=(long*)(dev0+0x114);
	temp = *ptr;

	// RAS-To-CAS (tRCD)
	int1 = temp | 0x70;
	if      (rcd == 2) { temp = int1 ^ 0x70; }
	else if (rcd == 3) { temp = int1 ^ 0x60; }
	else if (rcd == 4) { temp = int1 ^ 0x50; }
	else if (rcd == 5) { temp = int1 ^ 0x40; }
	// else		   { temp = temp;}

	//RAS precharge (tRP)
	int1 = temp | 0x7;
	if      (rp == 2) { temp = int1 ^ 0x7; }
	else if (rp == 3) { temp = int1 ^ 0x6; }
	else if (rp == 4) { temp = int1 ^ 0x5; }
	else if (rp == 5) { temp = int1 ^ 0x4; }
	// else		  { temp = temp;}

	if (mem_ctr[ctrl].device == 0x2770 )	// Lakeport?
	{
		// RAS Active to precharge (tRAS)
		int1 = temp | 0xF80000;	// bits 23:19
		if      (ras == 4)  { temp = int1 ^ 0xD80000; }
		else if (ras == 5)  { temp = int1 ^ 0xD00000; }
		else if (ras == 6)  { temp = int1 ^ 0xC80000; }
		else if (ras == 7)  { temp = int1 ^ 0xC00000; }
		else if (ras == 8)  { temp = int1 ^ 0xB80000; }
		else if (ras == 9)  { temp = int1 ^ 0xB00000; }
		else if (ras == 10) { temp = int1 ^ 0xA80000; }
		else if (ras == 11) { temp = int1 ^ 0xA00000; }
		else if (ras == 12) { temp = int1 ^ 0x980000; }
		else if (ras == 13) { temp = int1 ^ 0x900000; }
		else if (ras == 14) { temp = int1 ^ 0x880000; }
		else if (ras == 15) { temp = int1 ^ 0x800000; }
		// else		    { temp = temp;}
	}
	else
	{
		// RAS Active to precharge (tRAS)
		int1 = temp | 0xF00000;	// bits 23:20
		if      (ras == 4)  { temp = int1 ^ 0xB00000; }
		else if (ras == 5)  { temp = int1 ^ 0xA00000; }
		else if (ras == 6)  { temp = int1 ^ 0x900000; }
		else if (ras == 7)  { temp = int1 ^ 0x800000; }
		else if (ras == 8)  { temp = int1 ^ 0x700000; }
		else if (ras == 9)  { temp = int1 ^ 0x600000; }
		else if (ras == 10) { temp = int1 ^ 0x500000; }
		else if (ras == 11) { temp = int1 ^ 0x400000; }
		else if (ras == 12) { temp = int1 ^ 0x300000; }
		else if (ras == 13) { temp = int1 ^ 0x200000; }
		else if (ras == 14) { temp = int1 ^ 0x100000; }
		else if (ras == 15) { temp = int1 ^ 0x000000; }
		// else		    { temp = temp;}
	}

	// CAS Latency (tCAS)
	int1 = temp | 0x0300;
	if      (cas == 1) { temp = int1 ^ 0x200; }   // cas 2.5
	else if (cas == 2) { temp = int1 ^ 0x100; }
	else if (cas == 3) { temp = int1 ^ 0x300; }
	// else		   { temp = temp;}

	*ptr = temp;
	__delay(500);
	return;
}

void change_timing_Lakeport(int cas, int rcd, int rp, int ras)
{
	ulong int1, dev0, temp;
	long *ptr;

	//read MMRBAR
	pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
	dev0 &= 0xFFFFC000;

	ptr=(long*)(dev0+0x114);
	temp = *ptr;

	// RAS-To-CAS (tRCD)
	int1 = temp | 0x70;
	if      (rcd == 2) { temp = int1 ^ 0x70; }
	else if (rcd == 3) { temp = int1 ^ 0x60; }
	else if (rcd == 4) { temp = int1 ^ 0x50; }
	else if (rcd == 5) { temp = int1 ^ 0x40; }
	// else		   { temp = temp;}

	//RAS precharge (tRP)
	int1 = temp | 0x7;
	if      (rp == 2) { temp = int1 ^ 0x7; }
	else if (rp == 3) { temp = int1 ^ 0x6; }
	else if (rp == 4) { temp = int1 ^ 0x5; }
	else if (rp == 5) { temp = int1 ^ 0x4; }
	// else		  { temp = temp;}


	// CAS Latency (tCAS)
	int1 = temp | 0x0300;
	if      (cas == 1) { temp = int1 ^ 0x200; }   // cas 2.5
	else if (cas == 2) { temp = int1 ^ 0x100; }
	else if (cas == 3) { temp = int1 ^ 0x300; }
	// else		   { temp = temp;}

	*ptr = temp;
	__delay(500);
	return;
}

void change_timing_i875(int cas, int rcd, int rp, int ras){

	ulong int1, dev6, temp;
	long *ptr;

	/* Read the MMR Base Address & Define the pointer from the BAR6 overflow register */
	pci_conf_read( 0, 6, 0, 0x10, 4, &dev6);

	ptr=(long*)(dev6+0x60);

	temp = *ptr;

	// RAS-To-CAS (tRCD)
	int1 = temp | 0xC;
	if      (rcd == 2) { temp = int1 ^ 0x4; }
	else if (rcd == 3) { temp = int1 ^ 0x8; }
	else if (rcd == 4) { temp = int1 ^ 0xC; }
	else if (rcd == 5) { temp = int1 ^ 0xC; }
	// else		   { temp = temp;}


	//RAS precharge (tRP)
	int1 = temp | 0x3;
	if      (rp == 2) { temp = int1 ^ 0x1; }
	else if (rp == 3) { temp = int1 ^ 0x2; }
	else if (rp == 4) { temp = int1 ^ 0x3; }
	else if (rp == 5) { temp = int1 ^ 0x3; }
	// else		  { temp = temp;}


	// RAS Active to precharge (tRAS)
	int1 = temp | 0x380;
	if      (ras == 5)  { temp = int1 ^ 0x100; }
	else if (ras == 6)  { temp = int1 ^ 0x180; }
	else if (ras == 7)  { temp = int1 ^ 0x200; }
	else if (ras == 8)  { temp = int1 ^ 0x280; }
	else if (ras == 9)  { temp = int1 ^ 0x300; }
	else if (ras == 10) { temp = int1 ^ 0x380; }
	// else		    { temp = temp;}

	// CAS Latency (tCAS)
	int1 = temp | 0x60;
	if      (cas == 1) { temp = int1 ^ 0x60; }   // cas 2.5
	else if (cas == 2) { temp = int1 ^ 0x40; }
	else if (cas == 3) { temp = int1 ^ 0x20; }
	// else		   { temp = temp; }

	*ptr = temp;
	__delay(500);
	return;
}


void change_timing_nf2(int cas, int rcd, int rp, int ras) {

	ulong dramtlr, dramtlr2;
	ulong int1, int2;

	pci_conf_read(0, 0, 1, 0x90, 4, &dramtlr);
	pci_conf_read(0, 0, 1, 0xA0, 4, &dramtlr2);


	// CAS Latency (tCAS)
	int1 = dramtlr2 | 0x0070;
	if      (cas == 1) { int2 = int1 ^ 0x10; }  // cas = 2.5
	else if (cas == 2) { int2 = int1 ^ 0x50; }
	else if (cas == 3) { int2 = int1 ^ 0x40; }
	else		   { int2 = dramtlr2; }

	pci_conf_write(0, 0, 1, 0xA0, 4, int2);

	// RAS-To-CAS (tRCD)

	int1 = dramtlr | 0x700000;
	if      (rcd == 2) { int2 = int1 ^ 0x500000; }
	else if (rcd == 3) { int2 = int1 ^ 0x400000; }
	else if (rcd == 4) { int2 = int1 ^ 0x300000; }
	else if (rcd == 5) { int2 = int1 ^ 0x200000; }
	else if (rcd == 6) { int2 = int1 ^ 0x100000; }
	else		   { int2 = dramtlr;}


	// RAS Precharge (tRP)
	int1 = int2 | 0x70000000;
	if      (rp == 2) { int2 = int1 ^ 0x50000000; }
	else if (rp == 3) { int2 = int1 ^ 0x40000000; }
	else if (rp == 4) { int2 = int1 ^ 0x30000000; }
	else if (rp == 5) { int2 = int1 ^ 0x20000000; }
	else if (rp == 6) { int2 = int1 ^ 0x10000000; }
	// else		  { int2 = int2;}


	// RAS Active to precharge (tRAS)

	int1 = int2 | 0x78000;
	if      (ras == 4)  { int2 = int1 ^ 0x58000; }
	else if (ras == 5)  { int2 = int1 ^ 0x50000; }
	else if (ras == 6)  { int2 = int1 ^ 0x48000; }
	else if (ras == 7)  { int2 = int1 ^ 0x40000; }
	else if (ras == 8)  { int2 = int1 ^ 0x38000; }
	else if (ras == 9)  { int2 = int1 ^ 0x30000; }
	else if (ras == 10) { int2 = int1 ^ 0x28000; }
	else if (ras == 11) { int2 = int1 ^ 0x20000; }
	else if (ras == 12) { int2 = int1 ^ 0x18000; }
	else if (ras == 13) { int2 = int1 ^ 0x10000; }
	else if (ras == 14) { int2 = int1 ^ 0x08000; }
	// else		    { int2 = int2;}


	pci_conf_write(0, 0, 1, 0x90, 4, int2);
	__delay(500);
}


void change_timing_amd64(int cas, int rcd, int rp, int ras) {

	ulong dramtlr;
	ulong int1= 0x0;

	pci_conf_read(0, 24, 2, 0x88, 4, &dramtlr);

	// RAS-To-CAS (tRCD)
	int1 = dramtlr | 0x7000;
	if      (rcd == 2) { dramtlr = int1 ^ 0x5000; }
	else if (rcd == 3) { dramtlr = int1 ^ 0x4000; }
	else if (rcd == 4) { dramtlr = int1 ^ 0x3000; }
	else if (rcd == 5) { dramtlr = int1 ^ 0x2000; }
	else if (rcd == 6) { dramtlr = int1 ^ 0x1000; }
	else if (rcd == 1) { dramtlr = int1 ^ 0x6000; }
	// else		   { dramtlr = dramtlr;}


	//RAS precharge (tRP)
	int1 = dramtlr | 0x7000000;
	if      (rp == 2) { dramtlr = int1 ^ 0x5000000; }
	else if (rp == 3) { dramtlr = int1 ^ 0x4000000; }
	else if (rp == 1) { dramtlr = int1 ^ 0x6000000; }
	else if (rp == 4) { dramtlr = int1 ^ 0x3000000; }
	else if (rp == 5) { dramtlr = int1 ^ 0x2000000; }
	else if (rp == 6) { dramtlr = int1 ^ 0x1000000; }
	// else		  { dramtlr = dramtlr;}


	// RAS Active to precharge (tRAS)
	int1 = dramtlr | 0xF00000;
	if      (ras == 5)  { dramtlr = int1 ^ 0xA00000; }
	else if (ras == 6)  { dramtlr = int1 ^ 0x900000; }
	else if (ras == 7)  { dramtlr = int1 ^ 0x800000; }
	else if (ras == 8)  { dramtlr = int1 ^ 0x700000; }
	else if (ras == 9)  { dramtlr = int1 ^ 0x600000; }
	else if (ras == 10) { dramtlr = int1 ^ 0x500000; }
	else if (ras == 11) { dramtlr = int1 ^ 0x400000; }
	else if (ras == 12) { dramtlr = int1 ^ 0x300000; }
	else if (ras == 13) { dramtlr = int1 ^ 0x200000; }
	else if (ras == 14) { dramtlr = int1 ^ 0x100000; }
	// else		    { dramtlr = dramtlr;}


	// CAS Latency (tCAS)
	int1 = dramtlr | 0x7;	// some changes will cause the system hang, tried Draminit to no avail
	if      (cas == 1) { dramtlr = int1 ^ 0x2; }   // cas 2.5
	else if (cas == 2) { dramtlr = int1 ^ 0x6; }
	else if (cas == 3) { dramtlr = int1 ^ 0x5; }
	else if (cas == 4) { dramtlr = int1 ^ 0x7; } //cas 1.5 on a64
	// else		   { dramtlr = dramtlr; }

//	pci_conf_read(0, 24, 2, 0x90, 4, &dramcr);// use dram init
	pci_conf_write(0, 24, 2, 0x88, 4, dramtlr);
	__delay(500);

////////////////////////////////////////////////////////////////
// trying using the draminit, but do not work
}

// copy from lib.c code to add delay to chipset timing modification
void __delay(ulong loops)
{
	int d0;
	__asm__ __volatile__(
		"\tjmp 1f\n"
		".align 16\n"
		"1:\tjmp 2f\n"
		".align 16\n"
		"2:\tdecl %0\n\tjns 2b"
		:"=&a" (d0)
		:"0" (loops));
}

void amd64_tweak(int rwt, int wrt, int ref, int en2t, int rct, int rrd, int rwqb, int wr)
{
	ulong dramtlr;
	ulong int1= 0x0;

	pci_conf_read(0, 24, 2, 0x88, 4, &dramtlr);

	// Row Cycle time
	int1 = dramtlr | 0xF0;
	if      (rct == 7 ) { dramtlr = int1 ^ 0xF0; }
	else if (rct == 8 ) { dramtlr = int1 ^ 0xE0; }
	else if (rct == 9 ) { dramtlr = int1 ^ 0xD0; }
	else if (rct == 10) { dramtlr = int1 ^ 0xC0; }
	else if (rct == 11) { dramtlr = int1 ^ 0xB0; }
	else if (rct == 12) { dramtlr = int1 ^ 0xA0; }
	else if (rct == 13) { dramtlr = int1 ^ 0x90; }
	else if (rct == 14) { dramtlr = int1 ^ 0x80; }
	else if (rct == 15) { dramtlr = int1 ^ 0x70; }
	else if (rct == 16) { dramtlr = int1 ^ 0x60; }
	else if (rct == 17) { dramtlr = int1 ^ 0x50; }
	else if (rct == 18) { dramtlr = int1 ^ 0x40; }
	else if (rct == 19) { dramtlr = int1 ^ 0x30; }
	else if (rct == 20) { dramtlr = int1 ^ 0x20; }
	// else		    { dramtlr = dramtlr;}

	//Active-avtive ras-ras delay
	int1 = dramtlr | 0x70000;
	if      (rrd == 2) { dramtlr = int1 ^ 0x50000; } // 2 bus clocks
	else if (rrd == 3) { dramtlr = int1 ^ 0x40000; } // 3 bus clocks
	else if (rrd == 4) { dramtlr = int1 ^ 0x30000; } // 4 bus clocks
	// else		   { dramtlr = dramtlr;}

	//Write recovery time
	int1 = dramtlr | 0x10000000;
	if      (wr == 2) { dramtlr = int1 ^ 0x10000000; } // 2 bus clocks
	else if (wr == 3) { dramtlr = int1 ^ 0x00000000; } // 3 bus clocks
	// else		  { dramtlr = dramtlr;}

	pci_conf_write(0, 24, 2, 0x88, 4, dramtlr);
	__delay(500);
	//////////////////////////////////////////////

	pci_conf_read(0, 24, 2, 0x8C, 4, &dramtlr);

	// Write-to read delay
	int1 = dramtlr | 0x1;
	if      (wrt == 2) { dramtlr = int1 ^ 0x0; }
	else if (wrt == 1) { dramtlr = int1 ^ 0x1; }
	// else		   { dramtlr = dramtlr;}

	// Read-to Write delay
	int1 = dramtlr | 0x70;
	if      (rwt == 1) { dramtlr = int1 ^ 0x70; }
	else if (rwt == 2) { dramtlr = int1 ^ 0x60; }
	else if (rwt == 3) { dramtlr = int1 ^ 0x50; }
	else if (rwt == 4) { dramtlr = int1 ^ 0x40; }
	else if (rwt == 5) { dramtlr = int1 ^ 0x30; }
	else if (rwt == 6) { dramtlr = int1 ^ 0x20; }
	// else		   { dramtlr = dramtlr;}

	//Refresh Rate
	int1 = dramtlr | 0x1800;
	if      (ref == 1) { dramtlr = int1 ^ 0x1800; } // 15.6us
	else if (ref == 2) { dramtlr = int1 ^ 0x1000; } // 7.8us
	else if (ref == 3) { dramtlr = int1 ^ 0x0800; } // 3.9us
	// else		   { dramtlr = dramtlr;}

	pci_conf_write(0, 24, 2, 0x8c, 4, dramtlr);
	__delay(500);
	/////////////////////////////////////

	pci_conf_read(0, 24, 2, 0x90, 4, &dramtlr);

	// Enable 2t command
	int1 = dramtlr | 0x10000000;
	if      (en2t == 2) { dramtlr = int1 ^ 0x00000000; } // 2T
	else if (en2t == 1) { dramtlr = int1 ^ 0x10000000; } // 1T
	// else		    { dramtlr = dramtlr;}

	// Read Write queue bypass count
	int1 = dramtlr | 0xC000;
	if      (rwqb == 2)  { dramtlr = int1 ^ 0xC000; }
	else if (rwqb == 4)  { dramtlr = int1 ^ 0x8000; }
	else if (rwqb == 8)  { dramtlr = int1 ^ 0x4000; }
	else if (rwqb == 16) { dramtlr = int1 ^ 0x0000; }
	// else		     { dramtlr = dramtlr;}

	pci_conf_write(0, 24, 2, 0x90, 4, dramtlr);
	__delay(500);
	restart();
}