📄 bf533_ez-kit_flash_setup.asm
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/******************************************************************************/
//
// Name: BF533 EZ-KIT video ITU-656 receive mode (8bit) for the Omnivision chip OV6630
//
/*****************************************************************************************
(C) Copyright 2003 - Analog Devices, Inc. All rights reserved.
File Name: BF533_EZ-KIT_flash_setup.asm
Date Modified: 01/08/07 TL Rev 2.0
Software: VisualDSP++4.5, Assembler 1.1.0.2, Linker 3.8.0.2
Hardware: BF533 EZ-KIT Board (rev 1.2), Blackfin EZ-Extender (rev 1.2)
Chip: ADSP-BF533 REV 0.2
Special Connections: None
Purpose: To configure the flash for video devices
Program Parameters:
*********************************************************************************/
#include <defBF533.h>
/*****************************************************************************************/
// Global and extern subroutines
/*****************************************************************************************/
.global BF533_EZ_KIT_flash_setup;
/*****************************************************************************************/
// Program Define Section
/*****************************************************************************************/
//Setup of flash A on the EZ-KIT
// set asynch mem timing registers
//all banks enabled
#define en_async_mem 0xf
//all banks are configured in:
//4 cycles transition time; 3 cycles setup time; 2 cycles hold time;
//11 cycles read access time; 7 cycles write access time
#define amb0_timing 0x7bb0
#define amb1_timing 0x7bb0
#define amb2_timing 0x7bb0
#define amb3_timing 0x7bb0
#define flashA_sram 0x20240000 // base addr
#define flashA_csio 0x20270000 // base addr
#define portA_data_out 0x04 // offset
#define portB_data_out 0x05 // offset
#define portA_data_dir 0x06 // offset
#define portB_data_dir 0x07 // offset
/*****************************************************************************************/
// Program Variable Section
/*****************************************************************************************/
/*****************************************************************************************/
// Program
/*****************************************************************************************/
.section L1_code;
BF533_EZ_KIT_flash_setup:
//Async Memory Bank Control Register
p0.h = hi(EBIU_AMBCTL0);
p0.l = lo(EBIU_AMBCTL0);
r0.l = amb0_timing;
r0.h = amb1_timing;
[p0] = r0;
p0.h = hi(EBIU_AMBCTL1);
p0.l = lo(EBIU_AMBCTL1);
r0.l = amb2_timing;
r0.h = amb3_timing;
[p0] = r0;
//Async Memory Global Control Register
p0.h = hi(EBIU_AMGCTL);
p0.l = lo(EBIU_AMGCTL);
r0.l = w[p0];
r1 = en_async_mem;
r0 = r0 | r1;
w[p0] = r0;
ssync;
//Initialize flash A csio regs (port A)
// clear data registers
p1.h = hi(flashA_csio);
p1.l = lo(flashA_csio) + portA_data_out;
r0 = 0x0;
w[p1] = r0;
// direction control registers
p1.h = hi(flashA_csio);
p1.l = lo(flashA_csio) + portA_data_dir;
r0 = 0xFFFF(Z); // set dir=output
w[p1] = r0;
BF533_EZ_KIT_flash_setup.END:
RTS;
/**************************************************************************/
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