awgn_tb.vhd

为基带系统测试误码率而写的数字噪声程序

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--
-- Title       : Test Bench for awgn
-- Design      : lpm_lib
-- Author      : bird
-- Company     : ele
--
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--
-- File        : $DSN\src\TestBench\awgn_TB.vhd
-- Generated   : 2003-5-10, 18:59
-- From        : $DSN\src\AWGN.vhd
-- By          : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
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--
-- Description : Automatically generated Test Bench for awgn_tb
--
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library ieee;
use ieee.std_logic_1164.all;  

	-- Add your library and packages declaration here ...

entity awgn_tb is
end awgn_tb;

architecture TB_ARCHITECTURE of awgn_tb is
	-- Component declaration of the tested unit
	component awgn IS
	PORT(
	       clk: IN STD_LOGIC;	
	       reset: in std_logic;
	       asset: in std_logic;
	       state: in std_logic_vector(1 downto 0);
	       noise: out std_logic_vector(7 downto 0)	       
	);
	END component;		
	

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity

	signal clk : std_logic:='0';
	signal reset: std_logic;
	signal asset : std_logic:='0';
	signal state : std_logic_vector(1 downto 0):="00";
	signal noise : std_logic_vector(7 downto 0);
	

	-- Observed signals - signals mapped to the output ports of tested entity

	constant clk_cycle:time:=12.5ns;
        constant delay:time:=50ns;

	--
begin			

	clk<=not clk after clk_cycle/2;
	reset<='1','0' after delay;
	UUT : awgn
		port map (

			clk => clk,
			reset => reset,	 
			asset => asset,
			state => state,
			noise => noise
		);

	-- Add your stimulus here ...

end TB_ARCHITECTURE;