330_head.h

C8051F330部分模块程序,已经调试成功

/*---------------------------------------------------------------------------
;
;
;
;
; FILE NAME: C8051F330.H
; TARGET MCUs: C8051F330, F331
; DESCRIPTION: Register/bit definitions for the C8051F330 product family.
;
; REVISION 1.0
;
;---------------------------------------------------------------------------*/

/*  BYTE Registers  */

sfr p0            = 0x80; /* PORT 0 LATCH */
sfr sp            = 0x81; /* STACK POINTER */
sfr dpl           = 0x82; /* DATA POINTER LOW */
sfr dph           = 0x83; /* DATA POINTER HIGH */
sfr pcon          = 0x87; /* POWER CONTROL */
sfr tcon          = 0x88; /* TIMER/COUNTER CONTROL */
sfr tmod          = 0x89; /* TIMER/COUNTER MODE */
sfr tl0           = 0x8A; /* TIMER/COUNTER 0 LOW */
sfr tl1           = 0x8B; /* TIMER/COUNTER 1 LOW */
sfr th0           = 0x8C; /* TIMER/COUNTER 0 HIGH */
sfr th1           = 0x8D; /* TIMER/COUNTER 1 HIGH */
sfr ckcon         = 0x8E; /* CLOCK CONTROL */
sfr psctl         = 0x8F; /* PROGRAM STORE R/W CONTROL */
sfr p1            = 0x90; /* PORT 1 LATCH */
sfr tmr3cn        = 0x91; /* TIMER/COUNTER 3 CONTROL */
sfr tmr3rll       = 0x92; /* TIMER/COUNTER 3 RELOAD LOW */
sfr tmr3rlh       = 0x93; /* TIMER/COUNTER 3 RELOAD HIGH */
sfr tmr3l         = 0x94; /* TIMER/COUNTER 3 LOW */
sfr tmr3h         = 0x95; /* TIMER/COUNTER 3 HIGH */
sfr ida0l         = 0x96; /* CURRENT MODE DAC0 LOW */
sfr ida0h         = 0x97; /* CURRENT MODE DAC0 HIGH */
sfr scon0         = 0x98; /* UART0 CONTROL */
sfr sbuf0         = 0x99; /* UART0 DATA BUFFER */
sfr cpt0cn        = 0x9B; /* COMPARATOR0 CONTROL */
sfr cpt0md        = 0x9D; /* COMPARATOR0 MODE SELECTION */
sfr cpt0mx        = 0x9F; /* COMPARATOR0 MUX SELECTION */
sfr p2            = 0xA0; /* PORT 2 LATCH */
sfr spi0cfg       = 0xA1; /* SPI CONFIGURATION */
sfr spi0ckr       = 0xA2; /* SPI CLOCK RATE CONTROL */
sfr spi0dat       = 0xA3; /* SPI DATA */
sfr p0mdout       = 0xA4; /* PORT 0 OUTPUT MODE CONFIGURATION */
sfr p1mdout       = 0xA5; /* PORT 1 OUTPUT MODE CONFIGURATION */
sfr p2mdout       = 0xA6; /* PORT 2 OUTPUT MODE CONFIGURATION */
sfr ie            = 0xA8; /* INTERRUPT ENABLE */
sfr clksel        = 0xA9; /* CLOCK SELECT */
sfr emi0cn        = 0xAA; /* EXTERNAL MEMORY INTERFACE CONTROL */
sfr oscxcn        = 0xB1; /* EXTERNAL OSCILLATOR CONTROL */
sfr oscicn        = 0xB2; /* INTERNAL OSCILLATOR CONTROL */
sfr oscicl        = 0xB3; /* INTERNAL OSCILLATOR CALIBRATION */
sfr flscl         = 0xB6; /* FLASH SCALE */
sfr flkey         = 0xB7; /* FLASH LOCK AND KEY  */
sfr ip            = 0xB8; /* INTERRUPT PRIORITY */
sfr ida0cn        = 0xB9; /* CURRENT MODE DAC0 CONTROL */
sfr amx0n         = 0xBA; /* AMUX0 NEGATIVE CHANNEL SELECT */
sfr amx0p         = 0xBB; /* AMUX0 POSITIVE CHANNEL SELECT */
sfr adc0cf        = 0xBC; /* ADC0 CONFIGURATION */
sfr adc0l         = 0xBD; /* ADC0 LOW */
sfr adc0h         = 0xBE; /* ADC0 HIGH */
sfr smb0cn        = 0xC0; /* SMBUS CONTROL */
sfr smb0cf        = 0xC1; /* SMBUS CONFIGURATION */
sfr smb0dat       = 0xC2; /* SMBUS DATA */
sfr adc0gtl       = 0xC3; /* ADC0 GREATER-THAN COMPARE LOW */
sfr adc0gth       = 0xC4; /* ADC0 GREATER-THAN COMPARE HIGH */
sfr adc0ltl       = 0xC5; /* ADC0 LESS-THAN COMPARE WORD LOW */
sfr adc0lth       = 0xC6; /* ADC0 LESS-THAN COMPARE WORD HIGH */
sfr tmr2cn        = 0xC8; /* TIMER/COUNTER 2 CONTROL */
sfr tmr2rll       = 0xCA; /* TIMER/COUNTER 2 RELOAD LOW */
sfr tmr2rlh       = 0xCB; /* TIMER/COUNTER 2 RELOAD HIGH */
sfr tmr2l         = 0xCC; /* TIMER/COUNTER 2 LOW */
sfr tmr2h         = 0xCD; /* TIMER/COUNTER 2 HIGH */
sfr psw           = 0xD0; /* PROGRAM STATUS WORD */
sfr ref0cn        = 0xD1; /* VOLTAGE REFERENCE CONTROL */
sfr p0skip        = 0xD4; /* PORT 0 SKIP */
sfr p1skip        = 0xD5; /* PORT 1 SKIP */
sfr pca0cn        = 0xD8; /* PCA CONTROL */
sfr pca0md        = 0xD9; /* PCA MODE  */
sfr pca0cpm0      = 0xDA; /* PCA MODULE 0 MODE REGISTER */
sfr pca0cpm1      = 0xDB; /* PCA MODULE 1 MODE REGISTER */
sfr pca0cpm2      = 0xDC; /* PCA MODULE 2 MODE REGISTER */
sfr acc           = 0xE0; /* ACCUMULATOR */
sfr xbr0         = 0xE1; /* PORT I/O CROSSBAR CONTROL 0 */
sfr xbr1          = 0xE2; /* PORT I/O CROSSBAR CONTROL 1 */
sfr osclcn        = 0xE3; /* LOW-FREQUENCY OSCILLATOR CONTROL */
sfr it01cf        = 0xE4; /* INT0/INT1 CONFIGURATION */
sfr eie1          = 0xE6; /* EXTENDED INTERRUPT ENABLE 1 */
sfr adc0cn        = 0xE8; /* ADC0 CONTROL */
sfr pca0cpl1      = 0xE9; /* PCA CAPTURE 1 LOW */
sfr pca0cph1      = 0xEA; /* PCA CAPTURE 1 HIGH */
sfr pca0cpl2      = 0xEB; /* PCA CAPTURE 2 LOW */
sfr pca0cph2      = 0xEC; /* PCA CAPTURE 2 HIGH */
sfr rstsrc        = 0xEF; /* RESET SOURCE CONFIGURATION/STATUS */
sfr b             = 0xF0; /* B REGISTER */
sfr p0mdin        = 0xF1; /* PORT 0 INPUT MODE CONFIGURATION */
sfr p1mdin        = 0xF2; /* PORT 1 INPUT MODE CONFIGURATION */
sfr eip1          = 0xF6; /* EXTENDED INTERRUPT PRIORITY 1 */
sfr spi0cn        = 0xF8; /* SPI CONTROL */
sfr pca0l         = 0xF9; /* PCA COUNTER LOW */
sfr pca0h         = 0xFA; /* PCA COUNTER HIGH */
sfr pca0cpl0      = 0xFB; /* PCA CAPTURE 0 LOW */
sfr pca0cph0      = 0xFC; /* PCA CAPTURE 0 HIGH */
sfr vdm0cn        = 0xFF; /* VDD MONITOR CONTROL */



/* Bit Definitions */

/* TCON 0x88 */
sbit tf1 =        0x8F ;  /* TIMER 1 OVERFLOW FLAG */
sbit tr1 =        0x8E ;  /* TIMER 1 ON/OFF CONTROL */
sbit tf0 =        0x8D ;  /* TIMER 0 OVERFLOW FLAG */
sbit tr0 =        0x8C ;  /* TIMER 0 ON/OFF CONTROL */
sbit ie1 =        0x8B ;  /* EXT. INTERRUPT 1 EDGE FLAG */
sbit it1 =        0x8A ;  /* EXT. INTERRUPT 1 TYPE */
sbit ie0 =        0x89 ;  /* EXT. INTERRUPT 0 EDGE FLAG */
sbit it0 =        0x88 ;  /* EXT. INTERRUPT 0 TYPE */

/* SCON0 0x98 */
sbit s0mode =     0x9F ;  /* UART 0 MODE */
sbit mce0 =       0x9D ;  /* UART 0 MCE */
sbit ren0 =       0x9C ;  /* UART 0 RX ENABLE */
sbit tb80 =       0x9B ;  /* UART 0 TX BIT 8 */
sbit rb80 =       0x9A ;  /* UART 0 RX BIT 8 */
sbit ti0 =        0x99 ;  /* UART 0 TX INTERRUPT FLAG */
sbit ri0 =        0x98 ;  /* UART 0 RX INTERRUPT FLAG */

/* IE 0xA8 */
sbit ea =         0xAF ;  /* GLOBAL INTERRUPT ENABLE */
sbit espi0 =      0xAE ;  /* SPI0 INTERRUPT ENABLE */
sbit et2  =       0xAD ;  /* TIMER 2 INTERRUPT ENABLE */
sbit es0  =       0xAC ;  /* UART0 INTERRUPT ENABLE */
sbit et1 =        0xAB ;  /* TIMER 1 INTERRUPT ENABLE */
sbit ex1 =        0xAA ;  /* EXTERNAL INTERRUPT 1 ENABLE */
sbit et0 =        0xA9 ;  /* TIMER 0 INTERRUPT ENABLE */
sbit ex0 =        0xA8 ;  /* EXTERNAL INTERRUPT 0 ENABLE */

/* IP 0xB8 */
sbit pspi0 =      0xBE ;  /* SPI0 PRIORITY */
sbit pt2 =        0xBD ;  /* TIMER 2 PRIORITY */
sbit ps0 =        0xBC ;  /* UART0 PRIORITY */
sbit pt1 =        0xBB ;  /* TIMER 1 PRIORITY */
sbit px1 =        0xBA ;  /* EXTERNAL INTERRUPT 1 PRIORITY */
sbit pt0 =        0xB9 ;  /* TIMER 0 PRIORITY */
sbit px0 =        0xB8 ;  /* EXTERNAL INTERRUPT 0 PRIORITY */

/* SMB0CN 0xC0 */
sbit master =     0xC7 ;  /* SMBUS 0 MASTER/SLAVE */
sbit txmode =     0xC6 ;  /* SMBUS 0 TRANSMIT MODE */
sbit sta  =       0xC5 ;  /* SMBUS 0 START FLAG */
sbit sto =        0xC4 ;  /* SMBUS 0 STOP FLAG */
sbit ackrq =      0xC3 ;  /* SMBUS 0 ACKNOWLEDGE REQUEST */
sbit arblost =    0xC2 ;  /* SMBUS 0 ARBITRATION LOST */
sbit ack =        0xC1 ;  /* SMBUS 0 ACKNOWLEDGE FLAG */
sbit si =         0xC0 ;  /* SMBUS 0 INTERRUPT PENDING FLAG */

/* TMR2CN 0xC8 */
sbit tf2h =       0xCF ;  /* TIMER 2 HIGH BYTE OVERFLOW FLAG */
sbit tf2l =       0xCE ;  /* TIMER 2 LOW BYTE OVERFLOW FLAG */
sbit tf2len =     0xCD ;  /* TIMER 2 LOW BYTE INTERRUPT ENABLE */
sbit tf2cen =     0xCC ;  /* TIMER 2 LFO CAPTURE ENABLE */
sbit t2split =    0xCB ;  /* TIMER 2 SPLIT MODE ENABLE */
sbit tr2 =        0xCA ;  /* TIMER 2 ON/OFF CONTROL */
sbit t2xclk =     0xC8 ;  /* TIMER 2 EXTERNAL CLOCK SELECT */

/* PSW 0xD0 */
sbit cy =         0xD7 ;  /* CARRY FLAG */
sbit ac =         0xD6 ;  /* AUXILIARY CARRY FLAG */
sbit f0 =         0xD5 ;  /* USER FLAG 0 */
sbit rs1 =        0xD4 ;  /* REGISTER BANK SELECT 1 */
sbit rs0 =        0xD3 ;  /* REGISTER BANK SELECT 0 */
sbit ov =         0xD2 ;  /* OVERFLOW FLAG */
sbit f1 =         0xD1 ;  /* USER FLAG 1 */
sbit p =          0xD0 ;  /* ACCUMULATOR PARITY FLAG */

/* PCA0CN 0xD8 */
sbit cf =         0xDF ;  /* PCA 0 COUNTER OVERFLOW FLAG */
sbit cr =         0xDE ;  /* PCA 0 COUNTER RUN CONTROL BIT */
sbit ccf2 =       0xDA ;  /* PCA 0 MODULE 2 INTERRUPT FLAG */
sbit ccf1 =       0xD9 ;  /* PCA 0 MODULE 1 INTERRUPT FLAG */
sbit ccf0 =       0xD8 ;  /* PCA 0 MODULE 0 INTERRUPT FLAG */
                          /* ADC 0 WINDOW INTERRUPT FLAG */
/* ADC0CN 0xE8 */
sbit ad0en  =     0xEF ;  /* ADC 0 ENABLE */
sbit ad0tm =      0xEE ;  /* ADC 0 TRACK MODE */
sbit ad0int =     0xED ;  /* ADC 0 EOC INTERRUPT FLAG */
sbit ad0busy =    0xEC ;  /* ADC 0 BUSY FLAG */
sbit ad0wint =    0xEB ;  /* ADC 0 WINDOW INTERRUPT FLAG */
sbit ad0cm2 =     0xEA ;  /* ADC 0 CONVERT START MODE BIT 2 */
sbit ad0cm1   =   0xE9 ;  /* ADC 0 CONVERT START MODE BIT 1 */
sbit ad0cm0 =     0xE8 ;  /* ADC 0 CONVERT START MODE BIT 0 */

/* SPI0CN 0xF8 */
sbit spif =       0xFF ;  /* SPI 0 INTERRUPT FLAG */
sbit wcol =       0xFE ;  /* SPI 0 WRITE COLLISION FLAG */
sbit modf =       0xFD ;  /* SPI 0 MODE FAULT FLAG */
sbit rxovrn =     0xFC ;  /* SPI 0 RX OVERRUN FLAG */
sbit nssmd1 =     0xFB ;  /* SPI 0 SLAVE SELECT MODE 1 */
sbit nssmd0 =     0xFA ;  /* SPI 0 SLAVE SELECT MODE 0 */
sbit txbmt =      0xF9 ;  /* SPI 0 TX BUFFER EMPTY FLAG */
sbit spien =      0xF8 ;  /* SPI 0 SPI ENABLE */