clk.c

以TI 公司的OMAP5910为例

//////////////////////////////////////////////////////////////////////////
//            Copyright (C) 2004, Eyoka @ Microunit
//                           All Rights Reserved
//________________________________________________________________________
//
// FILENAME:    clk.c
// PROJECT:     High-Resolution Video System On OMAP
// MODULE:      MPU System
// DESCRIPTION: Clock Generation and System Reset Management Interface
// TARGET CPU:  ARM-925T of OMAP5910
// VERSION:     0.2
//________________________________________________________________________
//
// REVISE HISTORY
// DATE         VERSION AUTHOR  DESCRIPTION
// 2004-11-08   0.2     Eyoka   Checked.
// 2004-11-01   0.1     Eyoka   Created.
//////////////////////////////////////////////////////////////////////////

#include "clk.h"


/////////////////////////////////////////////////////////////////////
// FUNCTIONS
/////////////////////////////////////////////////////////////////////

//___________________________________________________________________
// Function: CLK_Init
// Usage: Initialize clock generation settings.
// Parameters:		N/A
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_Init(void)
{
	CLK_SetMode(SYNC_SCAL);

	CLK_SetDIV_DSPMMU(DIV_2);
	CLK_SetDIV_TC(DIV_2);
	CLK_SetDIV_DSP(DIV_1);
	CLK_SetDIV_ARM(DIV_1);
	CLK_SetDIV_LCD(DIV_2);
	CLK_SetDIV_PER(DIV_4);

	if(!CLK_SetupDPLL(20, 1, 10000))
	{
		puts("lock DPLL failed!");
	}

	RST_ReleasePER();

	CLK_EnableAPICK(TRUE);
	CLK_EnableXORCK(TRUE);
}

//___________________________________________________________________
// Function: CLK_SetupDPLL
// Usage: Config the DPLL to get proper clock frequency.
// Parameters:
//	mult			multiplier, 2<=mult<=25
//	divd			divider, 1<=divd<=4
//	timeout			timeout value to wait for DPLL to be locked.
// Return Values:
//	BOOL			TRUE if successfully locked, FALSE otherwise
//___________________________________________________________________
// do not support multpier 0 or 1
BOOL CLK_SetupDPLL(int mult, int divd, int timeout)
{
	if((mult<1) || (mult>25))
	{
		return FALSE;
	}

	if((divd<1) || (divd>4))
	{
		return FALSE;
	}
	divd--;

	// Setup PLL_MULT,PLL_DIV and disable
	DPLL1_CTL_REG = ((mult<<7)|(divd<<5)) | (DPLL1_CTL_REG & 0xF00F);
	// Enable
	DPLL1_CTL_REG |= 0x0010;
	// Wait locking
	while((timeout--) && !(DPLL1_CTL_REG & 0x0001))
	{
		;	//empty loop
	}

	if(DPLL1_CTL_REG & 0x0001)
	{
		return TRUE;
	}
	else
	{
		return FALSE;
	}
}

//___________________________________________________________________
// Function: CLK_SetDIV_DSPMMU
// Usage: Set DSPMMU clock divider
// Parameters:
//	divd			can be: DIV_1, DIV_2, DIV_4 or DIV_8
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_SetDIV_DSPMMU(CLK_DIV_t divd)
{
	ARM_CKCTL = (divd<<10) | (ARM_CKCTL&0xF3FF);
}

//___________________________________________________________________
// Function: CLK_SetDIV_TC
// Usage: Set traffic controler clock divider
// Parameters:
//	divd			can be: DIV_1, DIV_2, DIV_4 or DIV_8
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_SetDIV_TC(CLK_DIV_t divd)
{
	ARM_CKCTL = (divd<<8) | (ARM_CKCTL&0xFCFF);
}

//___________________________________________________________________
// Function: CLK_SetDIV_DSP
// Usage: Set DSP clock divider
// Parameters:
//	divd			can be: DIV_1, DIV_2, DIV_4 or DIV_8
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_SetDIV_DSP(CLK_DIV_t divd)
{
	ARM_CKCTL = (divd<<6) | (ARM_CKCTL&0xFF3F);
}

//___________________________________________________________________
// Function: CLK_SetDIV_ARM
// Usage: Set MPU clock divider
// Parameters:
//	divd			can be: DIV_1, DIV_2, DIV_4 or DIV_8
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_SetDIV_ARM(CLK_DIV_t divd)
{
	ARM_CKCTL = (divd<<4) | (ARM_CKCTL&0xFFCF);
}

//___________________________________________________________________
// Function: CLK_SetDIV_LCD
// Usage: Set LCD-controller clock divider
// Parameters:
//	divd			can be: DIV_1, DIV_2, DIV_4 or DIV_8
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_SetDIV_LCD(CLK_DIV_t divd)
{
	ARM_CKCTL = (divd<<2) | (ARM_CKCTL&0xFFF3);
}

//___________________________________________________________________
// Function: CLK_SetDIV_PER
// Usage: Set peripheral clock divider.
// Parameters:
//	divd			can be: DIV_1, DIV_2, DIV_4 or DIV_8
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_SetDIV_PER(CLK_DIV_t divd)
{
	ARM_CKCTL = divd | (ARM_CKCTL&0xFFFC);
}


//___________________________________________________________________
// Function: CLK_EnableDSPCK
// Usage: Enable/Disable the DSP clock (DSP_CK).
// Parameters:
//	bEnable			TRUE to Enable, FALSE to Disable.
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_EnableDSPCK(BOOL bEnable)
{
	ARM_CKCTL = (bEnable<<13) | (ARM_CKCTL&0xDFFF);
}

//___________________________________________________________________
// Function: CLK_EnableGPIOCK
// Usage: Enable/Disable the MPU-GPIO clock (connected to TIPB).
// Parameters:
//	bEnable			TRUE to Enable, FALSE to Disable.
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_EnableGPIOCK(BOOL bEnable)
{
	ARM_IDLECT2 = (bEnable<<9) | (ARM_IDLECT2&0xFDFF);
}

//___________________________________________________________________
// Function: CLK_EnableDMAREQCK
// Usage: Enable/Disable the permanently-supplied-clock to the
//        DMA controller to function on a clock-request basis.
// Parameters:
//	bEnable			TRUE to Enable, FALSE to Disable.
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_EnableDMAREQCK(BOOL bEnable)
{
	ARM_IDLECT2 = (bEnable<<8) | (ARM_IDLECT2&0xFEFF);
}

//___________________________________________________________________
// Function: CLK_EnableTIMCK
// Usage: Enable/Disable the MPU-timer clock (connected to TIPB).
// Parameters:
//	bEnable			TRUE to Enable, FALSE to Disable.
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_EnableTIMCK(BOOL bEnable)
{
	ARM_IDLECT2 = (bEnable<<7) | (ARM_IDLECT2&0xFF7F);
}

//___________________________________________________________________
// Function: CLK_EnableAPICK
// Usage: Enable/Disable the MPUI clock.
// Parameters:
//	bEnable			TRUE to Enable, FALSE to Disable.
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_EnableAPICK(BOOL bEnable)
{
	ARM_IDLECT2 = (bEnable<<6) | (ARM_IDLECT2&0xFFBF);
}

//___________________________________________________________________
// Function: CLK_EnableLBCK
// Usage: Enable/Disable the local bus clock.
// Parameters:
//	bEnable			TRUE to Enable, FALSE to Disable.
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_EnableLBCK(BOOL bEnable)
{
	ARM_IDLECT2 = (bEnable<<4) | (ARM_IDLECT2&0xFFEF);
}

//___________________________________________________________________
// Function: CLK_EnableLCDCK
// Usage: Enable/Disable the LCD-controller clock (connected to TIPB).
// Parameters:
//	bEnable			TRUE to Enable, FALSE to Disable.
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_EnableLCDCK(BOOL bEnable)
{
	ARM_IDLECT2 = (bEnable<<3) | (ARM_IDLECT2&0xFFF7);
}

//___________________________________________________________________
// Function: CLK_EnablePERCK
// Usage: Enable/Disable the peripheral clock (MPUPER_CK).
// Parameters:
//	bEnable			TRUE to Enable, FALSE to Disable.
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_EnablePERCK(BOOL bEnable)
{
	ARM_IDLECT2 = (bEnable<<2) | (ARM_IDLECT2&0xFFFB);
}

//___________________________________________________________________
// Function: CLK_EnableXORCK
// Usage: Enable/Disable the OS-timer clock(XORP_CK).
// Parameters:
//	bEnable			TRUE to Enable, FALSE to Disable.
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_EnableXORCK(BOOL bEnable)
{
	ARM_IDLECT2 = (bEnable<<1) | (ARM_IDLECT2&0xFFFD);
}

//___________________________________________________________________
// Function: CLK_EnableWDTCK
// Usage: Enable/Disable the watchdog timer clock (connected to TIPB).
// Parameters:
//	bEnable			TRUE to Enable, FALSE to Disable.
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_EnableWDTCK(BOOL bEnable)
{
	ARM_IDLECT2 = (bEnable) | (ARM_IDLECT2&0xFFFE);
}

//___________________________________________________________________
// Function: RST_SoftReset
// Usage: Software reset the MPU.
// Parameters:		N/A
// Return Values:	N/A
//___________________________________________________________________
//
void RST_SoftReset(void)
{
	ARM_RSTCT1 |= 0x0008;
}

//___________________________________________________________________
// Function: RST_ReleaseDSP
// Usage: Release DSP from reset.
// Parameters:		N/A
// Return Values:	N/A
//___________________________________________________________________
//
void RST_ReleaseDSP(void)
{
	ARM_RSTCT1 |= 0x0004;
}

//___________________________________________________________________
// Function: RST_ResetDSP
// Usage: Reset the DSP.
// Parameters:		N/A
// Return Values:	N/A
//___________________________________________________________________
//
void RST_ResetDSP(void)
{
	ARM_RSTCT1 &= 0xFFFD;
}

//___________________________________________________________________
// Function: RST_EnableDSP
// Usage: Enables the DSP.
// Parameters:		N/A
// Return Values:	N/A
//___________________________________________________________________
//
void RST_EnableDSP(void)
{
	ARM_RSTCT1 |= 0x0002;
}

//___________________________________________________________________
// Function: RST_ResetARM
// Usage: Reset the MPU.
// Parameters:		N/A
// Return Values:	N/A
//___________________________________________________________________
//
void RST_ResetARM(void)
{
	ARM_RSTCT1 |= 0x0001;
}

//___________________________________________________________________
// Function: RST_ResetPER
// Usage: Reset the MPU Peripherals.
// Parameters:		N/A
// Return Values:	N/A
//___________________________________________________________________
//
void RST_ResetPER(void)
{
	ARM_RSTCT2 = 0x0000;
}

//___________________________________________________________________
// Function: RST_ReleasePER
// Usage: Release MPU Peripherals from reset.
// Parameters:		N/A
// Return Values:	N/A
//___________________________________________________________________
//
void RST_ReleasePER(void)
{
	ARM_RSTCT2 = 0x0001;
}

//___________________________________________________________________
// Function: CLK_SetMode
// Usage: Set clock mode
// Parameters:
//	mode			can be: FULL_SYNC or SYNC_SCAL.
// Return Values:	N/A
//___________________________________________________________________
//
void CLK_SetMode(CLK_MODE_t mode)
{
	ARM_SYSST = (mode<<12) | (ARM_SYSST&0x07FF);
}



// the end
//////////////////////////////////////////////////////////////////////////