dspdma.c

以TI 公司的OMAP5910为例

//////////////////////////////////////////////////////////////////////////
//            Copyright (C) 2004, Eyoka @ Microunit
//                           All Rights Reserved
//________________________________________________________________________
//
// FILENAME:    dspdma.c
// PROJECT:     High-Resolution Video System On OMAP
// MODULE:      DSP System
// DESCRIPTION: DSP DMA support.
// TARGET CPU:  DSP-C55xx of OMAP5910
// VERSION:     1.2
//________________________________________________________________________
//
// REVISE HISTORY
// DATE         VERSION AUTHOR  DESCRIPTION
// 2004-10-13   1.2     Eyoka   Added: DMA_Wait#, DMA_DA2SD
//                              Renamed: DMA_ReadRAW -> DMA_SD2DA
// 2004-10-09   1.1     Eyoka   ioport_pointer replaced by REG.
// 2004-09-28   1.0     Eyoka   First release.
//////////////////////////////////////////////////////////////////////////

#include "dspdma.h"


/////////////////////////////////////////////////////////////////////
// DMA FUNCTIONS
/////////////////////////////////////////////////////////////////////

//___________________________________________________________________
// Function: DMA_SD2DA
// Usage: DMA transfer from SDRAM to DARAM using channel-0
// Parameters:
//    inBuf			out	- input buffer(DMA destination)
//    src_addr			- source BYTE address
//    size				- size in WORD address
// Return Values:
//    N/A
//___________________________________________________________________
//
void DMA_SD2DA(WORD *inBuf, DWORD src_addr, WORD size)
{
	// DMA use BYTE address
	DWORD dst_addr = (DWORD)inBuf<<1;

	// address registers
	DMA_CSSA_L0 = (WORD)src_addr;
	DMA_CSSA_U0 = (WORD)(src_addr>>16);
	DMA_CDSA_L0 = (WORD)dst_addr;
	DMA_CDSA_U0 = (WORD)(dst_addr>>16);

	// frame/element count registers
	DMA_CEN0 = size;
	DMA_CFN0 = 1;
	
	// frame/element index registers
//	DMA_CSEI0 = 1; not used
//	DMA_CSFI0 = 1; not used
//	DMA_CDEI0 = 1; not used
//	DMA_CDFI0 = 1; not used

	// source destination parameters
	///////////////////////////////////////////////////////
	// 15-14	DSTBEN		10		Enable
	// 13		DSTPACK		0		Disable
	// 12-9		DST			0001	DARAM
	// 8-7		SRCBEN		10		Enable
	// 6		SRCPACK		0		Disable
	// 5-2		SRC			0010	SDRAM
	// 1-0		DATATYPE	01		16 bit
	///////////////////////////////////////////////////////
	DMA_CSDP0 = 0x8309;

	// wait for last transfer done
	while(DMA_CCR0 & 0x0080)
	{
		;		// empty loop
	}	

	// channel control register
	/////////////////////////////////////////////////////
	// 15-14	DSTAMODE	01		Automatic
	// 13-12	SRCAMODE	01		Automatic
	// 11		ENDPROG		1		Ready
	// 10		RESERVED	0		-
	// 9		REPEAT		0		Disable
	// 8		AUTOINIT	0		Disable
	// 7		EN			1		Start DMA
	// 6		PRIO		0		Low
	// 5		FS			0		-
	// 4-0		SYNC		00000	-
	/////////////////////////////////////////////////////
	DMA_CCR0 = 0x5880;
	// transfer started
}

//___________________________________________________________________
// Function: DMA_DA2SD
// Usage: DMA transfer from DARAM to SDRAM using channel-2
// Parameters:
//    addrLCD		out	- destination BYTE address
//    dst_addr			- output buffer(DMA source)
//    size				- size in WORD address
// Return Values:
//    N/A
//___________________________________________________________________
//
void DMA_DA2SD(DWORD dst_addr, WORD *outBuf, WORD size)

{
	// DMA use BYTE address
	DWORD src_addr = (DWORD)outBuf<<1;

	// address registers
	DMA_CSSA_L2 = (WORD)src_addr;
	DMA_CSSA_U2 = (WORD)(src_addr>>16);
	DMA_CDSA_L2 = (WORD)dst_addr;
	DMA_CDSA_U2 = (WORD)(dst_addr>>16);

	// frame/element count registers
	DMA_CEN2 = size;
	DMA_CFN2 = 1;

	// frame/element index registers
//	DMA_CSEI2 = 1;	not used
//	DMA_CSFI2 = 1;	not used
//	DMA_CDEI2 = 1;	not used
//	DMA_CDFI2 = 1;	not used

	// source destination parameters register
	///////////////////////////////////////////////////////
	// 15-14	DSTBEN		10		Enable
	// 13		DSTPACK		0		Disable
	// 12-9		DST			0010	SDRAM
	// 8-7		SRCBEN		10		Enable
	// 6		SRCPACK		0		Disable
	// 5-2		SRC			0001	DARAM
	// 1-0		DATATYPE	01		16 bit
	///////////////////////////////////////////////////////
	DMA_CSDP2 = 0x8505;

	// wait for last transfer done
	while(DMA_CCR2 & 0x0080)
	{
		;		// empty loop
	}

	// channel control register
	/////////////////////////////////////////////////////
	// 15-14	DSTAMODE	01		Automatic post increment
	// 13-12	SRCAMODE	01		Automatic post increment
	// 11		ENDPROG		1		Ready
	// 10		RESERVED	0		-
	// 9		REPEAT		0		Disable
	// 8		AUTOINIT	0		Disable
	// 7		EN			1		Start DMA
	// 6		PRIO		1		High
	// 5		FS			0		-
	// 4-0		SYNC		00000	-
	/////////////////////////////////////////////////////
	DMA_CCR2 = 0x58C0;
	// transfer started
}

void DMA_SA2SD(DWORD dst_addr, WORD *outBuf, WORD size)
{
	// DMA use BYTE address
	DWORD src_addr = (DWORD)outBuf<<1;

	// address registers
	DMA_CSSA_L1 = (WORD)src_addr;
	DMA_CSSA_U1 = (WORD)(src_addr>>16);
	DMA_CDSA_L1 = (WORD)dst_addr;
	DMA_CDSA_U1 = (WORD)(dst_addr>>16);

	// frame/element count registers
	DMA_CEN1 = size;
	DMA_CFN1 = 1;

	// frame/element index registers
//	DMA_CSEI2 = 1;	not used
//	DMA_CSFI2 = 1;	not used
//	DMA_CDEI2 = 1;	not used
//	DMA_CDFI2 = 1;	not used

	// source destination parameters register
	///////////////////////////////////////////////////////
	// 15-14	DSTBEN		10		Enable
	// 13		DSTPACK		0		Disable
	// 12-9		DST			0010	SDRAM
	// 8-7		SRCBEN		10		Enable
	// 6		SRCPACK		0		Disable
	// 5-2		SRC			0000	SARAM
	// 1-0		DATATYPE	01		16 bit
	///////////////////////////////////////////////////////
	DMA_CSDP1 = 0x8501;

	// wait for last transfer done
	while(DMA_CCR1 & 0x0080)
	{
		;		// empty loop
	}

	// channel control register
	/////////////////////////////////////////////////////
	// 15-14	DSTAMODE	01		Automatic post increment
	// 13-12	SRCAMODE	01		Automatic post increment
	// 11		ENDPROG		1		Ready
	// 10		RESERVED	0		-
	// 9		REPEAT		0		Disable
	// 8		AUTOINIT	0		Disable
	// 7		EN			1		Start DMA
	// 6		PRIO		1		High
	// 5		FS			0		-
	// 4-0		SYNC		00000	-
	/////////////////////////////////////////////////////
	DMA_CCR1 = 0x58C0;
	// transfer started
}

//___________________________________________________________________
// Function: DMA_WriteJPG
// Usage: Write encoded buffer(@SARAM) to result JPG location(@SDRAM)
//        using DMA channel-1
// Parameters:
//    addrJPG		out	- BYTE address of result JPG location
//    outBuf			- pointer to output buffer
//    size				- size in BYTE address
// Return Values:
//    N/A
//___________________________________________________________________
//
void DMA_WriteJPG(DWORD addrJPG, WORD *outBuf, WORD size)
{
	// DMA use BYTE address
	DWORD src_addr = ((DWORD)outBuf<<1) + 1;
	DWORD dst_addr = addrJPG;

	// address registers
	DMA_CSSA_L1 = (WORD)src_addr;
	DMA_CSSA_U1 = (WORD)(src_addr>>16);
	DMA_CDSA_L1 = (WORD)dst_addr;
	DMA_CDSA_U1 = (WORD)(dst_addr>>16);

	// frame/element count registers
	DMA_CEN1 = size;
	DMA_CFN1 = 1;
	
	// frame/element index registers
	DMA_CSEI1 = 2;
//	DMA_CSFI1 = 1; not used
//	DMA_CDEI1 = 1; not used
//	DMA_CDFI1 = 1; not used

	// source destination parameters register
	///////////////////////////////////////////////////////
	// 15-14	DSTBEN		10		Enable
	// 13		DSTPACK		1		Enable
	// 12-9		DST			0010	SDRAM
	// 8-7		SRCBEN		00		Disable
	// 6		SRCPACK		1		Enable
	// 5-2		SRC			0000	SARAM
	// 1-0		DATATYPE	00		8 bit
	///////////////////////////////////////////////////////
	DMA_CSDP1 = 0xA440;

	// wait for last transfer done
	while(DMA_CCR1 & 0x0080)
	{
		;		// empty loop
	}

	// channel control register
	///////////////////////////////////////////////////////
	// 15-14	DSTAMODE	01		Automatic post increment
	// 13-12	SRCAMODE	10		Single index
	// 11		ENDPROG		1		Ready
	// 10		RESERVED	0		-
	// 9		REPEAT		0		Disable
	// 8		AUTOINIT	0		Disable
	// 7		EN			1		Start DMA
	// 6		PRIO		1		High
	// 5		FS			0		-
	// 4-0		SYNC		00000	-
	///////////////////////////////////////////////////////
	DMA_CCR1 = 0x68C0;
	// transfer started
}


// the end
//////////////////////////////////////////////////////////////////////////