dspdma.h

以TI 公司的OMAP5910为例

//////////////////////////////////////////////////////////////////////////
//            Copyright (C) 2004, Eyoka @ Microunit
//                           All Rights Reserved
//________________________________________________________________________
//
// FILENAME:    dspdma.h
// PROJECT:     High-Resolution Video System On OMAP
// MODULE:      DSP System
// DESCRIPTION: DSP DMA support.
// TARGET CPU:  DSP-C55xx of OMAP5910
// VERSION:     1.2
//________________________________________________________________________
//
// REVISE HISTORY
// DATE         VERSION AUTHOR  DESCRIPTION
// 2004-10-13   1.2     Eyoka   Added: DMA_Wait#, DMA_DA2SD
//                              Renamed: DMA_ReadRAW -> DMA_SD2DA
// 2004-10-09   1.1     Eyoka   ioport_pointer replaced by REG.
// 2004-09-27   1.0     Eyoka   First release.
//////////////////////////////////////////////////////////////////////////

#ifndef _DSPDMA_H_
#define _DSPDMA_H_

#include "datatypes.h"


/////////////////////////////////////////////////////////////////////
// DMA REGISTERS
/////////////////////////////////////////////////////////////////////

//---------------------------------------------------------
// GLOBAL
//---------------------------------------------------------

// Global control
#define	DMA_GCR			REG(0x0E00)
// Global time-out control
#define	DMA_GTCR		REG(0x0E01)
// Global software incompatible control
#define	DMA_GSCR		REG(0x0E02)

//---------------------------------------------------------
// CHANNEL 0
//---------------------------------------------------------

// Channel 0 source destination parameters
#define	DMA_CSDP0		REG(0x0C00)
// Channel 0 control
#define	DMA_CCR0		REG(0x0C01)
// Channel 0 interrupt control
#define	DMA_CICR0		REG(0x0C02)
// Channel 0 status
#define	DMA_CSR0		REG(0x0C03)
// Channel 0 source start address, lower bits
#define	DMA_CSSA_L0		REG(0x0C04)
// Channel 0 source start address, upper bits
#define	DMA_CSSA_U0		REG(0x0C05)
// Channel 0 destination start address, lower bits
#define	DMA_CDSA_L0		REG(0x0C06)
// Channel 0 destination start address, upper bits
#define	DMA_CDSA_U0		REG(0x0C07)
// Channel 0 element number
#define	DMA_CEN0		REG(0x0C08)
// Channel 0 frame number
#define	DMA_CFN0		REG(0x0C09)
// Channel 0 source frame index
#define	DMA_CSFI0		REG(0x0C0A)
// Channel 0 source element index
#define	DMA_CSEI0		REG(0x0C0B)
// Channel 0 source address counter
#define	DMA_CSAC0		REG(0x0C0C)
// Channel 0 destination address counter
#define	DMA_CDAC0		REG(0x0C0D)
// Channel 0 destination element index
#define	DMA_CDEI0		REG(0x0C0E)
// Channel 0 destination frame index
#define	DMA_CDFI0		REG(0x0C0F)

//---------------------------------------------------------
// CHANNEL 1
//---------------------------------------------------------

// Channel 1 source destination parameters
#define	DMA_CSDP1		REG(0x0C20)
// Channel 1 control
#define	DMA_CCR1		REG(0x0C21)
// Channel 1 interrupt control
#define	DMA_CICR1		REG(0x0C22)
// Channel 1 status
#define	DMA_CSR1		REG(0x0C23)
// Channel 1 source start address, lower bits
#define	DMA_CSSA_L1		REG(0x0C24)
// Channel 1 source start address, upper bits
#define	DMA_CSSA_U1		REG(0x0C25)
// Channel 1 destination start address, lower bits
#define	DMA_CDSA_L1		REG(0x0C26)
// Channel 1 destination start address, upper bits
#define	DMA_CDSA_U1		REG(0x0C27)
// Channel 1 element number
#define	DMA_CEN1		REG(0x0C28)
// Channel 1 frame number
#define	DMA_CFN1		REG(0x0C29)
// Channel 1 source frame index
#define	DMA_CSFI1		REG(0x0C2A)
// Channel 1 source element index
#define	DMA_CSEI1		REG(0x0C2B)
// Channel 1 source address counter
#define	DMA_CSAC1		REG(0x0C2C)
// Channel 1 destination address counter
#define	DMA_CDAC1		REG(0x0C2D)
// Channel 1 destination element index
#define	DMA_CDEI1		REG(0x0C2E)
// Channel 1 destination frame index
#define	DMA_CDFI1		REG(0x0C2F)

//---------------------------------------------------------
// CHANNEL 2
//---------------------------------------------------------

// Channel 2 source destination parameters
#define	DMA_CSDP2		REG(0x0C40)
// Channel 2 control
#define	DMA_CCR2		REG(0x0C41)
// Channel 2 interrupt control
#define	DMA_CICR2		REG(0x0C42)
// Channel 2 status
#define	DMA_CSR2		REG(0x0C43)
// Channel 2 source start address, lower bits
#define	DMA_CSSA_L2		REG(0x0C44)
// Channel 2 source start address, upper bits
#define	DMA_CSSA_U2		REG(0x0C45)
// Channel 2 destination start address, lower bits
#define	DMA_CDSA_L2		REG(0x0C46)
// Channel 2 destination start address, upper bits
#define	DMA_CDSA_U2		REG(0x0C47)
// Channel 2 element number
#define	DMA_CEN2		REG(0x0C48)
// Channel 2 frame number
#define	DMA_CFN2		REG(0x0C49)
// Channel 2 source frame index
#define	DMA_CSFI2		REG(0x0C4A)
// Channel 2 source element index
#define	DMA_CSEI2		REG(0x0C4B)
// Channel 2 source address counter
#define	DMA_CSAC2		REG(0x0C4C)
// Channel 2 destination address counter
#define	DMA_CDAC2		REG(0x0C4D)
// Channel 2 destination element index
#define	DMA_CDEI2		REG(0x0C4E)
// Channel 2 destination frame index
#define	DMA_CDFI2		REG(0x0C4F)


/////////////////////////////////////////////////////////////////////
// DMA FUNCTIONS
/////////////////////////////////////////////////////////////////////

//___________________________________________________________________
// Function: DMA_SD2DA
// Usage: DMA transfer from SDRAM to DARAM using channel-0
// Parameters:
//    inBuf			out	- input buffer(DMA destination)
//    src_addr			- source BYTE address
//    size				- size in WORD address
// Return Values:
//    N/A
//___________________________________________________________________
//
void DMA_SD2DA(WORD *inBuf, DWORD src_addr, WORD size);

//___________________________________________________________________
// Function: DMA_DA2SD
// Usage: DMA transfer from DARAM to SDRAM using channel-2
// Parameters:
//    addrLCD		out	- destination BYTE address
//    dst_addr			- output buffer(DMA source)
//    size				- size in WORD address
// Return Values:
//    N/A
//___________________________________________________________________
//
void DMA_DA2SD(DWORD dst_addr, WORD *outBuf, WORD size);

void DMA_SA2SD(DWORD dst_addr, WORD *outBuf, WORD size);

//___________________________________________________________________
// Function: DMA_WriteJPG
// Usage: Write encoded buffer(@SARAM) to result JPG location(@SDRAM)
//        using DMA channel-1
// Parameters:
//    addrJPG		out	- BYTE address of result JPG location
//    outBuf			- pointer to output buffer
//    size				- size in BYTE address
// Return Values:
//    N/A
//___________________________________________________________________
//
void DMA_WriteJPG(DWORD addrJPG, WORD *outBuf, WORD size);

//___________________________________________________________________
// Function: DMA_Wait0
// Usage: Wait untill transfer of channel-0 is done
// Parameters:
//    N/A
// Return Values:
//    N/A
//___________________________________________________________________
//
inline void DMA_Wait0(void)
{
	while(DMA_CCR0 & 0x0080)
	{
		;		// empty loop
	}
}

//___________________________________________________________________
// Function: DMA_Wait1
// Usage: Wait untill transfer of channel-1 is done
// Parameters:
//    N/A
// Return Values:
//    N/A
//___________________________________________________________________
//
inline void DMA_Wait1(void)
{
	while(DMA_CCR1 & 0x0080)
	{
		;		// empty loop
	}
}

//___________________________________________________________________
// Function: DMA_Wait2
// Usage: Wait untill transfer of channel-2 is done
// Parameters:
//    N/A
// Return Values:
//    N/A
//___________________________________________________________________
//
inline void DMA_Wait2(void)
{
	while(DMA_CCR2 & 0x0080)
	{
		;		// empty loop
	}
}



#endif // #ifndef _DSPDMA_H_