dccn10.vhd

来自「基于MAXPLUS II 的软件设计」· VHDL 代码 · 共 32 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity dccn10 is
 port( q: in bit_vector(3 downto 0);
       dateout :out std_logic_vector(7 downto 0);
      seiout: out std_logic_vector(7 downto 0));
 end dccn10;
architecture beha of dccn10 is
begin
process(q)
begin
 case q is
when "0000"=>dateout<="00111111";seiout<="00100000";
when "0001"=>dateout<="01111101";seiout<="00100000";
when "0010"=>dateout<="00111111";seiout<="00100000";
when "0011"=>dateout<="00000110";seiout<="00100000";
when "0100"=>dateout<="00111111";seiout<="00100000";
when "0101"=>dateout<="01011011";seiout<="00100000";
when "0110"=>dateout<="00111111";seiout<="00100000";
when "0111"=>dateout<="01111101";seiout<="00100000";
when "1000"=>dateout<="00111111";seiout<="00100000";
when "1001"=>dateout<="00111111";seiout<="00100000";
when others =>dateout<="00111111";seiout<="00000000";
end case;
end process;
end beha ;