cnt3.vhd

来自「基于MAXPLUS II 的软件设计」· VHDL 代码 · 共 21 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity cnt3 is
 port(clk,nrst:in std_logic ;
             q:buffer std_logic_vector(2 downto 0));
 end cnt3;

architecture behav of cnt3 is
begin
process(clk,nrst)
begin
if(clk'event and clk='1') then
  if( nrst='0') then q<="000" ;
  else q<=q+'1' ;
end if;
end if;
end process;
end behav;