cn10.vhd

来自「基于MAXPLUS II 的软件设计」· VHDL 代码 · 共 24 行

library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
entity cn10 is
 port(clk,clrn, en1:in std_logic ;
             q:buffer std_logic_vector(3 downto 0));
 end cn10;

architecture behav of cn10 is
begin
process(clk,clrn)
begin
if(clrn='0')then q<="0000";
  elsif(clk'event and clk='1') then
   if( en1='1') then  
    if(q="1001")then q<="0000";
    else q<=q+'1' ;
    end if;
   end if;
end if;
end process;
end behav;