state.vhd

这是一个用VHDL +图形法在CPLD内部搭建的液晶显示的驱动程序。液晶是ocmj5*10系列

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY state IS
  PORT (clk             :IN std_logic;
        clk1            :IN std_logic;
        flag            :IN std_logic; 
        busy            :IN std_logic;
        row             :IN std_logic_vector(2 DOWNTO 0);
        data_in         :IN std_logic_vector(7 DOWNTO 0);
        req             :OUT std_logic;      
        read_add        :OUT std_logic_vector(4 DOWNTO 0);
        data_out        :OUT std_logic_vector(7 DOWNTO 0);
        clear           :OUT std_logic;
        write_out       :OUT std_logic;
        state_out       :OUT std_logic_vector(3 DOWNTO 0)
       );
END state;
ARCHITECTURE behave OF state IS
  TYPE state IS (s_b,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
  SIGNAL current_state,next_state: state  :=s_b;
SHARED VARIABLE addr,addr1          : std_logic_vector(4 DOWNTO 0) :="00000";
SHARED VARIABLE  i,ii           : integer :=0;
SIGNAL clear1           : std_logic :='0';
SHARED VARIABLE      write:            std_logic:='0';
--signal point :std_logic :='0';
BEGIN        
 

 PROCESS(clk)   
   BEGIN
     --IF we='1' THEN
       -- clear<='1';
    --  ELSE clear<=clear1;  
     -- end if;  
      --addr:=conv_std_logic_vector(i, 5);
      --read_add<=addr;
      
   IF clk='1' AND clk'event THEN
  

     IF flag='1' THEN
       --  point<='1';
         clear1<='0';
       CASE current_state IS
         WHEN s_b=>
             state_out<="1111";
          IF data_in<"10100000" then
             next_state<=s0;
          ELSIF "10100000"<data_in and data_in<"11110000" THEN
            next_state<=s4;
          ELSE  
            next_state<=s9;
          END IF;
         WHEN s0=>
             state_out<="0000"; 
          IF busy='0' AND write='0' THEN 
             data_out<="11111001";
             req<='1';
             write:='1';
             next_state<=s0;
          ELSIF busy='1' AND write='1' THEN
             req<='0';
             next_state<=s1;
             write:='0';
          ELSE next_state<=s0;
          END IF;
         WHEN s1=>
             state_out<="0001"; 
          IF busy='0' AND write='0' THEN 
             data_out<="000"&addr;
             req<='1';
             write:='1';
             next_state<=s1;
          ELSIF busy='1' AND write='1' THEN
             req<='0';
             next_state<=s2;
             write:='0';
          ELSE next_state<=s1;
          END IF;
         WHEN s2=>
             state_out<="0010"; 
          IF busy='0' AND write='0' THEN 
             data_out<=conv_std_logic_vector(((conv_integer("00000"&row))*16),8);
             req<='1';
             write:='1';
             next_state<=s2; 
          ELSIF busy='1' AND write='1' THEN
             req<='0';
             next_state<=s3;
             write:='0';
          ELSE next_state<=s2;
          END IF;

         WHEN s3=>
             state_out<="0011";
          IF busy='0' AND write='0' THEN  
             data_out<=data_in;
             req<='1';
             write:='1';
             next_state<=s3; 
          ELSIF busy='1' and write='1' THEN
             req<='0';
             next_state<=s_b;
             write:='0';
             IF i<=18 THEN
              i:=i+1;
                -- clear1<='0';
             ELSE i:=0;
                  clear1<='1';
             end IF;
          ELSE next_state<=s3;
          END IF;         
        WHEN s4=>
            state_out<="0100";
          IF busy='0' AND write='0' THEN 
             data_out<="11110000";
             req<='1';
             write:='1';
             next_state<=s4;
          ELSIF busy='1' AND write='1' THEN
             req<='0';
             write:='0';
             next_state<=s5;
          ELSE next_state<=s4;
          END IF;
        WHEN s5=>
            state_out<="0101";
          IF busy='0' AND write='0' THEN 
             ii:=i/2;
             addr1:=conv_std_logic_vector(ii, 5);
             read_add<=addr; 
             data_out<="000"&addr1;
             req<='1';
             write:='1';
             next_state<=s5;
          ELSIF busy='1' AND write='1' THEN
             req<='0';
             next_state<=s6;
             write:='0';
          ELSE next_state<=s5;
          END IF;
        WHEN s6=>
              state_out<="0110";
          IF busy='0' AND write='0' THEN 
             data_out<="00000"&row;
             req<='1';
             write:='1';
             next_state<=s6;
          ELSIF busy='1' AND write='1' THEN
             req<='0';
             next_state<=s7;
             write:='0';
          ELSE next_state<=s6;
          END IF;
        WHEN s7=>
             state_out<="0111";
          IF busy='0' AND write='0' THEN
             data_out<=data_in-160;
             req<='1';
             write:='1';
             next_state<=s7;
          ELSIF busy='1' AND write='1' THEN
             req<='0';
             i:=i+1;
             next_state<=s8;
             write:='0';
          ELSE next_state<=s7;
          END IF;
        WHEN s8=>
             state_out<="1000";
          IF busy='0' AND write='0' THEN 
             data_out<=data_in-160;
             req<='1';
             write:='1';
             next_state<=s8;
          ELSIF busy='1' AND write='1' THEN
             req<='0';
             next_state<=s_b;
             write:='0';
               
             IF i<=18 THEN
              i:=i+1;
              --clear1<='0';
             ELSE i:=0;
                   clear1<='1';
             end IF;
          ELSE next_state<=s8;
          END IF;
         WHEN S9=>
             state_out<="1001";
          IF busy='0' AND write='0' THEN 
             data_out<=data_in;
             req<='1';
             write:='1';
             next_state<=s9;
          ELSIF busy='1' AND write='1' THEN
             req<='0';
             next_state<=s_b;
             write:='0';
             clear1<='1';
          ELSE next_state<=s9;
          END IF;
          
     END CASE;
    write_out<=write;
   END IF; 
END IF;
 addr:=conv_std_logic_vector(i, 5);
 read_add<=addr;
 current_state<=next_state;
END PROCESS;

p2:process(clk1)
begin
 if rising_edge(clk1) then
     
         clear<=clear1; 
 end if;
end process p2;
END behave;