ram.vhd

来自「这是一个用VHDL +图形法在CPLD内部搭建的液晶显示的驱动程序。液晶是ocm」· VHDL 代码 · 共 40 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY ram IS
	GENERIC
	(
		ADDRESS_WIDTH	: integer := 5;
		DATA_WIDTH	: integer := 8
	);
	PORT
	(   clk             : IN  std_logic;
	    data_in			: IN  std_logic_vector(7 DOWNTO 0);
		write_address	: IN  std_logic_vector(4 DOWNTO 0);
		read_address	: IN  std_logic_vector(4 DOWNTO 0);
		we			    : IN  std_logic;
		data_out		: OUT std_logic_vector(7 DOWNTO 0)
	);
END ram;

ARCHITECTURE ram OF ram IS
	TYPE ram IS ARRAY(0 TO 19) OF std_logic_vector(7 DOWNTO 0);

	SIGNAL ram_block : ram;
BEGIN
	PROCESS(clk,we,write_address)
	
	BEGIN
	   
	  IF clk='1' and clk'event THEN 
	        
			IF we='1' THEN
			   ram_block(to_integer(unsigned(write_address))) <= data_in;
			   
			END IF;
	    data_out<= ram_block(to_integer(unsigned(read_address)));
	  END IF;
	END PROCESS;
END ram;