freq.vhd

来自「这是一个用VHDL +图形法在CPLD内部搭建的液晶显示的驱动程序。液晶是ocm」· VHDL 代码 · 共 32 行

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity freq is
 PORT( clk  :  IN  STD_LOGIC;
       clk_out : OUT  STD_LOGIC 
      );
END freq;
ARCHITECTURE behave OF freq IS
 signal  i: integer range 0 to 359; 
 SIGNAL  Q: std_logic ;
begin
  
  process(clk)

    begin
    	 
     if clk'event and clk='1' then
         
       if i=359 then 
         Q<=NOT Q;
         i<=0;   
       else 
         i<=i+1;
	  end if;
    end if;
    clk_out<=Q ;
   end process;
  
end behave;