📄 lcd.map.rpt
字号:
; -- arithmetic mode ; 44 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 32 ;
; -- asynchronous clear/load mode ; 2 ;
; ; ;
; Total registers ; 330 ;
; Total logic cells in carry chains ; 47 ;
; I/O pins ; 115 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 275 ;
; Total fan-out ; 2210 ;
; Average fan-out ; 2.96 ;
+---------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
; |lcd ; 631 (36) ; 330 ; 0 ; 115 ; 0 ; 301 (36) ; 270 (0) ; 60 (0) ; 47 (0) ; 0 (0) ; |lcd ;
; |74373:inst3| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lcd|74373:inst3 ;
; |74373b:inst4| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lcd|74373b:inst4 ;
; |dd:inst10| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |lcd|dd:inst10 ;
; |freq:inst| ; 21 (21) ; 10 ; 0 ; 0 ; 0 ; 11 (11) ; 5 (5) ; 5 (5) ; 9 (9) ; 0 (0) ; |lcd|freq:inst ;
; |ram:inst1| ; 440 (440) ; 264 ; 0 ; 0 ; 0 ; 176 (176) ; 256 (256) ; 8 (8) ; 0 (0) ; 0 (0) ; |lcd|ram:inst1 ;
; |state:inst2| ; 115 (115) ; 54 ; 0 ; 0 ; 0 ; 61 (61) ; 8 (8) ; 46 (46) ; 38 (38) ; 0 (0) ; |lcd|state:inst2 ;
; |try:inst9| ; 2 (1) ; 1 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (0) ; 0 (0) ; 0 (0) ; |lcd|try:inst9 ;
; |DFF2:inst| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |lcd|try:inst9|DFF2:inst ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |lcd|state:inst2|next_state ;
+----------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+----------------+
; Name ; next_state.s9 ; next_state.s8 ; next_state.s7 ; next_state.s6 ; next_state.s5 ; next_state.s4 ; next_state.s3 ; next_state.s2 ; next_state.s1 ; next_state.s0 ; next_state.s_b ;
+----------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+----------------+
; next_state.s_b ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; next_state.s0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; next_state.s1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; next_state.s2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; next_state.s3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; next_state.s4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; next_state.s5 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; next_state.s6 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; next_state.s7 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; next_state.s8 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; next_state.s9 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+----------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+----------------+
+----------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------+----+
; Latch Name ; ;
+-----------------------------------------------+----+
; 74373:inst3|16 ; ;
; 74373:inst3|15 ; ;
; 74373:inst3|14 ; ;
; 74373:inst3|13 ; ;
; 74373:inst3|12 ; ;
; 74373:inst3|19 ; ;
; 74373:inst3|18 ; ;
; 74373:inst3|17 ; ;
; 74373b:inst4|19 ; ;
; 74373b:inst4|18 ; ;
; 74373b:inst4|17 ; ;
; 74373b:inst4|16 ; ;
; 74373b:inst4|15 ; ;
; 74373b:inst4|14 ; ;
; 74373b:inst4|13 ; ;
; 74373b:inst4|12 ; ;
; Number of user-specified and inferred latches ; 16 ;
+-----------------------------------------------+----+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 330 ;
; Number of registers using Synchronous Clear ; 32 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 2 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 308 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 8:1 ; 32 bits ; 160 LEs ; 32 LEs ; 128 LEs ; Yes ; |lcd|state:inst2|i[3] ;
; 11:1 ; 2 bits ; 14 LEs ; 6 LEs ; 8 LEs ; Yes ; |lcd|state:inst2|data_out[6] ;
; 11:1 ; 2 bits ; 14 LEs ; 6 LEs ; 8 LEs ; Yes ; |lcd|state:inst2|data_out[2] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: ram:inst1 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------+
; address_width ; 5 ; Untyped ;
; data_width ; 8 ; Untyped ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Jul 10 15:35:10 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd -c lcd
Info: Found 2 design units, including 1 entities, in source file drr/dd.vhd
Info: Found design unit 1: dd-behave
Info: Found entity 1: dd
Info: Found 1 design units, including 1 entities, in source file dready/try.bdf
Info: Found entity 1: try
Info: Found 2 design units, including 1 entities, in source file ram/ram.vhd
Info: Found design unit 1: ram-ram
Info: Found entity 1: ram
Info: Found 2 design units, including 1 entities, in source file state/state.vhd
Info: Found design unit 1: state-behave
Info: Found entity 1: state
Info: Found 2 design units, including 1 entities, in source file freq/freq.vhd
Info: Found design unit 1: freq-behave
Info: Found entity 1: freq
Info: Found 1 design units, including 1 entities, in source file lcd.bdf
Info: Found entity 1: lcd
Info: Elaborating entity "lcd" for the top level hierarchy
Warning: Pin "empty" not connected
Info: Elaborating entity "state" for hierarchy "state:inst2"
Warning (10492): VHDL Process Statement warning at state.vhd(214): signal "next_state" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "freq" for hierarchy "freq:inst"
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -