lcd.tan.qmsg

这是一个用VHDL +图形法在CPLD内部搭建的液晶显示的驱动程序。液晶是ocmj5*10系列

{ "Info" "ITAN_NO_REG2REG_EXIST" "xd\[12\] " "Info: No valid register-to-register data paths exist for clock \"xd\[12\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "xd\[10\] " "Info: No valid register-to-register data paths exist for clock \"xd\[10\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "xd\[11\] " "Info: No valid register-to-register data paths exist for clock \"xd\[11\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 4 " "Warning: Circuit may not operate. Detected 4 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "ram:inst1\|data_out\[7\] state:inst2\|next_state.s9 clk 1.007 ns " "Info: Found hold time violation between source  pin or register \"ram:inst1\|data_out\[7\]\" and destination pin or register \"state:inst2\|next_state.s9\" for clock \"clk\" (Hold time is 1.007 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.322 ns + Largest " "Info: + Largest clock skew is 4.322 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.141 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.141 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 275 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 275; CLK Node = 'clk'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 104 152 320 120 "clk" "" } { 184 992 1008 200 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns freq:inst\|Q 2 REG LC_X12_Y3_N8 54 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N8; Fanout = 54; REG Node = 'freq:inst\|Q'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.032 ns" { clk freq:inst|Q } "NODE_NAME" } "" } } { "freq/freq.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/freq/freq.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(0.918 ns) 8.141 ns state:inst2\|next_state.s9 3 REG LC_X11_Y8_N2 4 " "Info: 3: + IC(3.028 ns) + CELL(0.918 ns) = 8.141 ns; Loc. = LC_X11_Y8_N2; Fanout = 4; REG Node = 'state:inst2\|next_state.s9'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.946 ns" { freq:inst|Q state:inst2|next_state.s9 } "NODE_NAME" } "" } } { "state/state.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/state/state.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.46 % ) " "Info: Total cell delay = 3.375 ns ( 41.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.766 ns ( 58.54 % ) " "Info: Total interconnect delay = 4.766 ns ( 58.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "8.141 ns" { clk freq:inst|Q state:inst2|next_state.s9 } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "8.141 ns" { clk clk~combout freq:inst|Q state:inst2|next_state.s9 } { 0.000ns 0.000ns 1.738ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 275 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 275; CLK Node = 'clk'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 104 152 320 120 "clk" "" } { 184 992 1008 200 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns ram:inst1\|data_out\[7\] 2 REG LC_X10_Y8_N4 4 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y8_N4; Fanout = 4; REG Node = 'ram:inst1\|data_out\[7\]'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "2.656 ns" { clk ram:inst1|data_out[7] } "NODE_NAME" } "" } } { "ram/ram.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/ram/ram.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.819 ns" { clk ram:inst1|data_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout ram:inst1|data_out[7] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "8.141 ns" { clk freq:inst|Q state:inst2|next_state.s9 } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "8.141 ns" { clk clk~combout freq:inst|Q state:inst2|next_state.s9 } { 0.000ns 0.000ns 1.738ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.819 ns" { clk ram:inst1|data_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout ram:inst1|data_out[7] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "ram/ram.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/ram/ram.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.160 ns - Shortest register register " "Info: - Shortest register to register delay is 3.160 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram:inst1\|data_out\[7\] 1 REG LC_X10_Y8_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y8_N4; Fanout = 4; REG Node = 'ram:inst1\|data_out\[7\]'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "" { ram:inst1|data_out[7] } "NODE_NAME" } "" } } { "ram/ram.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/ram/ram.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.381 ns) + CELL(0.200 ns) 1.581 ns state:inst2\|process0~228 2 COMB LC_X11_Y8_N4 2 " "Info: 2: + IC(1.381 ns) + CELL(0.200 ns) = 1.581 ns; Loc. = LC_X11_Y8_N4; Fanout = 2; COMB Node = 'state:inst2\|process0~228'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "1.581 ns" { ram:inst1|data_out[7] state:inst2|process0~228 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.804 ns) 3.160 ns state:inst2\|next_state.s9 3 REG LC_X11_Y8_N2 4 " "Info: 3: + IC(0.775 ns) + CELL(0.804 ns) = 3.160 ns; Loc. = LC_X11_Y8_N2; Fanout = 4; REG Node = 'state:inst2\|next_state.s9'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "1.579 ns" { state:inst2|process0~228 state:inst2|next_state.s9 } "NODE_NAME" } "" } } { "state/state.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/state/state.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.004 ns ( 31.77 % ) " "Info: Total cell delay = 1.004 ns ( 31.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.156 ns ( 68.23 % ) " "Info: Total interconnect delay = 2.156 ns ( 68.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.160 ns" { ram:inst1|data_out[7] state:inst2|process0~228 state:inst2|next_state.s9 } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "3.160 ns" { ram:inst1|data_out[7] state:inst2|process0~228 state:inst2|next_state.s9 } { 0.000ns 1.381ns 0.775ns } { 0.000ns 0.200ns 0.804ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "state/state.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/state/state.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "8.141 ns" { clk freq:inst|Q state:inst2|next_state.s9 } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "8.141 ns" { clk clk~combout freq:inst|Q state:inst2|next_state.s9 } { 0.000ns 0.000ns 1.738ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.819 ns" { clk ram:inst1|data_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout ram:inst1|data_out[7] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.160 ns" { ram:inst1|data_out[7] state:inst2|process0~228 state:inst2|next_state.s9 } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "3.160 ns" { ram:inst1|data_out[7] state:inst2|process0~228 state:inst2|next_state.s9 } { 0.000ns 1.381ns 0.775ns } { 0.000ns 0.200ns 0.804ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ram:inst1\|ram_block~378 xa\[15\] clk 17.264 ns register " "Info: tsu for register \"ram:inst1\|ram_block~378\" (data pin = \"xa\[15\]\", clock pin = \"clk\") is 17.264 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.750 ns + Longest pin register " "Info: + Longest pin to register delay is 20.750 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns xa\[15\] 1 CLK PIN_22 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_22; Fanout = 1; CLK Node = 'xa\[15\]'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "" { xa[15] } "NODE_NAME" } "" } } { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 464 144 312 480 "xa\[15..12\]" "" } { 584 328 392 600 "xa\[15\]" "" } { 664 328 392 680 "xa\[13\]" "" } { 704 328 392 720 "xa\[12\]" "" } { 632 336 496 648 "xa\[14\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.309 ns) + CELL(0.511 ns) 2.952 ns inst16~29 2 COMB LC_X1_Y6_N0 1 " "Info: 2: + IC(1.309 ns) + CELL(0.511 ns) = 2.952 ns; Loc. = LC_X1_Y6_N0; Fanout = 1; COMB Node = 'inst16~29'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "1.820 ns" { xa[15] inst16~29 } "NODE_NAME" } "" } } { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 536 608 656 600 "inst16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.899 ns) + CELL(0.511 ns) 5.362 ns inst16 3 COMB LC_X2_Y7_N0 64 " "Info: 3: + IC(1.899 ns) + CELL(0.511 ns) = 5.362 ns; Loc. = LC_X2_Y7_N0; Fanout = 64; COMB Node = 'inst16'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "2.410 ns" { inst16~29 inst16 } "NODE_NAME" } "" } } { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 536 608 656 600 "inst16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.366 ns) 12.728 ns 74373:inst3\|15 4 COMB LOOP LC_X6_Y7_N7 18 " "Info: 4: + IC(0.000 ns) + CELL(7.366 ns) = 12.728 ns; Loc. = LC_X6_Y7_N7; Fanout = 18; COMB LOOP Node = '74373:inst3\|15'" { { "Info" "ITDB_PART_OF_SCC" "74373:inst3\|15 LC_X6_Y7_N7 " "Info: Loc. = LC_X6_Y7_N7; Node \"74373:inst3\|15\"" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "" { 74373:inst3|15 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "" { 74373:inst3|15 } "NODE_NAME" } "" } } { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 392 232 296 472 "15" "" } } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "7.366 ns" { inst16 74373:inst3|15 } "NODE_NAME" } "" } } { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 392 232 296 472 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.345 ns) + CELL(0.914 ns) 14.987 ns ram:inst1\|ram_block~8600 5 COMB LC_X6_Y7_N9 2 " "Info: 5: + IC(1.345 ns) + CELL(0.914 ns) = 14.987 ns; Loc. = LC_X6_Y7_N9; Fanout = 2; COMB Node = 'ram:inst1\|ram_block~8600'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "2.259 ns" { 74373:inst3|15 ram:inst1|ram_block~8600 } "NODE_NAME" } "" } } { "ram/ram.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/ram/ram.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.869 ns) + CELL(0.200 ns) 17.056 ns rtl~16 6 COMB LC_X5_Y5_N9 8 " "Info: 6: + IC(1.869 ns) + CELL(0.200 ns) = 17.056 ns; Loc. = LC_X5_Y5_N9; Fanout = 8; COMB Node = 'rtl~16'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "2.069 ns" { ram:inst1|ram_block~8600 rtl~16 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.451 ns) + CELL(1.243 ns) 20.750 ns ram:inst1\|ram_block~378 7 REG LC_X3_Y6_N6 1 " "Info: 7: + IC(2.451 ns) + CELL(1.243 ns) = 20.750 ns; Loc. = LC_X3_Y6_N6; Fanout = 1; REG Node = 'ram:inst1\|ram_block~378'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.694 ns" { rtl~16 ram:inst1|ram_block~378 } "NODE_NAME" } "" } } { "ram/ram.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/ram/ram.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.877 ns ( 57.24 % ) " "Info: Total cell delay = 11.877 ns ( 57.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.873 ns ( 42.76 % ) " "Info: Total interconnect delay = 8.873 ns ( 42.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db"