lcd.tan.qmsg

这是一个用VHDL +图形法在CPLD内部搭建的液晶显示的驱动程序。液晶是ocmj5*10系列

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register state:inst2\|i\[1\] register ram:inst1\|data_out\[7\] 66.38 MHz 15.064 ns Internal " "Info: Clock \"clk\" has Internal fmax of 66.38 MHz between source register \"state:inst2\|i\[1\]\" and destination register \"ram:inst1\|data_out\[7\]\" (period= 15.064 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.033 ns + Longest register register " "Info: + Longest register to register delay is 10.033 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state:inst2\|i\[1\] 1 REG LC_X8_Y5_N5 68 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y5_N5; Fanout = 68; REG Node = 'state:inst2\|i\[1\]'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "" { state:inst2|i[1] } "NODE_NAME" } "" } } { "state/state.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/state/state.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.958 ns) + CELL(0.740 ns) 3.698 ns ram:inst1\|ram_block~8442 2 COMB LC_X6_Y6_N5 1 " "Info: 2: + IC(2.958 ns) + CELL(0.740 ns) = 3.698 ns; Loc. = LC_X6_Y6_N5; Fanout = 1; COMB Node = 'ram:inst1\|ram_block~8442'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.698 ns" { state:inst2|i[1] ram:inst1|ram_block~8442 } "NODE_NAME" } "" } } { "ram/ram.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/ram/ram.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.212 ns) + CELL(0.200 ns) 5.110 ns ram:inst1\|ram_block~8443 3 COMB LC_X5_Y6_N3 1 " "Info: 3: + IC(1.212 ns) + CELL(0.200 ns) = 5.110 ns; Loc. = LC_X5_Y6_N3; Fanout = 1; COMB Node = 'ram:inst1\|ram_block~8443'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "1.412 ns" { ram:inst1|ram_block~8442 ram:inst1|ram_block~8443 } "NODE_NAME" } "" } } { "ram/ram.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/ram/ram.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.442 ns) + CELL(0.511 ns) 8.063 ns ram:inst1\|ram_block~8451 4 COMB LC_X9_Y8_N9 1 " "Info: 4: + IC(2.442 ns) + CELL(0.511 ns) = 8.063 ns; Loc. = LC_X9_Y8_N9; Fanout = 1; COMB Node = 'ram:inst1\|ram_block~8451'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "2.953 ns" { ram:inst1|ram_block~8443 ram:inst1|ram_block~8451 } "NODE_NAME" } "" } } { "ram/ram.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/ram/ram.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.166 ns) + CELL(0.804 ns) 10.033 ns ram:inst1\|data_out\[7\] 5 REG LC_X10_Y8_N4 4 " "Info: 5: + IC(1.166 ns) + CELL(0.804 ns) = 10.033 ns; Loc. = LC_X10_Y8_N4; Fanout = 4; REG Node = 'ram:inst1\|data_out\[7\]'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "1.970 ns" { ram:inst1|ram_block~8451 ram:inst1|data_out[7] } "NODE_NAME" } "" } } { "ram/ram.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/ram/ram.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.255 ns ( 22.48 % ) " "Info: Total cell delay = 2.255 ns ( 22.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.778 ns ( 77.52 % ) " "Info: Total interconnect delay = 7.778 ns ( 77.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "10.033 ns" { state:inst2|i[1] ram:inst1|ram_block~8442 ram:inst1|ram_block~8443 ram:inst1|ram_block~8451 ram:inst1|data_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "10.033 ns" { state:inst2|i[1] ram:inst1|ram_block~8442 ram:inst1|ram_block~8443 ram:inst1|ram_block~8451 ram:inst1|data_out[7] } { 0.000ns 2.958ns 1.212ns 2.442ns 1.166ns } { 0.000ns 0.740ns 0.200ns 0.511ns 0.804ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.322 ns - Smallest " "Info: - Smallest clock skew is -4.322 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 275 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 275; CLK Node = 'clk'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 104 152 320 120 "clk" "" } { 184 992 1008 200 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns ram:inst1\|data_out\[7\] 2 REG LC_X10_Y8_N4 4 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y8_N4; Fanout = 4; REG Node = 'ram:inst1\|data_out\[7\]'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "2.656 ns" { clk ram:inst1|data_out[7] } "NODE_NAME" } "" } } { "ram/ram.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/ram/ram.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.819 ns" { clk ram:inst1|data_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout ram:inst1|data_out[7] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.141 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.141 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 275 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 275; CLK Node = 'clk'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "" { clk } "NODE_NAME" } "" } } { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 104 152 320 120 "clk" "" } { 184 992 1008 200 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns freq:inst\|Q 2 REG LC_X12_Y3_N8 54 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N8; Fanout = 54; REG Node = 'freq:inst\|Q'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.032 ns" { clk freq:inst|Q } "NODE_NAME" } "" } } { "freq/freq.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/freq/freq.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(0.918 ns) 8.141 ns state:inst2\|i\[1\] 3 REG LC_X8_Y5_N5 68 " "Info: 3: + IC(3.028 ns) + CELL(0.918 ns) = 8.141 ns; Loc. = LC_X8_Y5_N5; Fanout = 68; REG Node = 'state:inst2\|i\[1\]'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.946 ns" { freq:inst|Q state:inst2|i[1] } "NODE_NAME" } "" } } { "state/state.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/state/state.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.46 % ) " "Info: Total cell delay = 3.375 ns ( 41.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.766 ns ( 58.54 % ) " "Info: Total interconnect delay = 4.766 ns ( 58.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "8.141 ns" { clk freq:inst|Q state:inst2|i[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "8.141 ns" { clk clk~combout freq:inst|Q state:inst2|i[1] } { 0.000ns 0.000ns 1.738ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.819 ns" { clk ram:inst1|data_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout ram:inst1|data_out[7] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "8.141 ns" { clk freq:inst|Q state:inst2|i[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "8.141 ns" { clk clk~combout freq:inst|Q state:inst2|i[1] } { 0.000ns 0.000ns 1.738ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "state/state.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/state/state.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "ram/ram.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/ram/ram.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "10.033 ns" { state:inst2|i[1] ram:inst1|ram_block~8442 ram:inst1|ram_block~8443 ram:inst1|ram_block~8451 ram:inst1|data_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "10.033 ns" { state:inst2|i[1] ram:inst1|ram_block~8442 ram:inst1|ram_block~8443 ram:inst1|ram_block~8451 ram:inst1|data_out[7] } { 0.000ns 2.958ns 1.212ns 2.442ns 1.166ns } { 0.000ns 0.740ns 0.200ns 0.511ns 0.804ns } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "3.819 ns" { clk ram:inst1|data_out[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout ram:inst1|data_out[7] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "8.141 ns" { clk freq:inst|Q state:inst2|i[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "8.141 ns" { clk clk~combout freq:inst|Q state:inst2|i[1] } { 0.000ns 0.000ns 1.738ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "xa\[12\] " "Info: No valid register-to-register data paths exist for clock \"xa\[12\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "xa\[13\] " "Info: No valid register-to-register data paths exist for clock \"xa\[13\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "xa\[15\] " "Info: No valid register-to-register data paths exist for clock \"xa\[15\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "xa\[14\] " "Info: No valid register-to-register data paths exist for clock \"xa\[14\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "xwe " "Info: No valid register-to-register data paths exist for clock \"xwe\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "xd\[8\] " "Info: No valid register-to-register data paths exist for clock \"xd\[8\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "xd\[9\] " "Info: No valid register-to-register data paths exist for clock \"xd\[9\]\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}