lcd.tan.qmsg

这是一个用VHDL +图形法在CPLD内部搭建的液晶显示的驱动程序。液晶是ocmj5*10系列

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "74373:inst3\|19 " "Info: Node \"74373:inst3\|19\"" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 744 232 296 824 "19" "" } } } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 744 232 296 824 "19" "" } } } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "74373:inst3\|15 " "Info: Node \"74373:inst3\|15\"" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 392 232 296 472 "15" "" } } } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 392 232 296 472 "15" "" } } } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "74373:inst3\|14 " "Info: Node \"74373:inst3\|14\"" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 304 232 296 384 "14" "" } } } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 304 232 296 384 "14" "" } } } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "74373:inst3\|16 " "Info: Node \"74373:inst3\|16\"" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 480 232 296 560 "16" "" } } } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 480 232 296 560 "16" "" } } } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "74373:inst3\|13 " "Info: Node \"74373:inst3\|13\"" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 216 232 296 296 "13" "" } } } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 216 232 296 296 "13" "" } } } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "74373:inst3\|12 " "Info: Node \"74373:inst3\|12\"" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 128 232 296 208 "12" "" } } } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 128 232 296 208 "12" "" } } } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 104 152 320 120 "clk" "" } { 184 992 1008 200 "clk" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "xa\[12\] " "Info: Assuming node \"xa\[12\]\" is an undefined clock" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 464 144 312 480 "xa\[15..12\]" "" } { 584 328 392 600 "xa\[15\]" "" } { 664 328 392 680 "xa\[13\]" "" } { 704 328 392 720 "xa\[12\]" "" } { 632 336 496 648 "xa\[14\]" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "xa\[12\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "xa\[13\] " "Info: Assuming node \"xa\[13\]\" is an undefined clock" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 464 144 312 480 "xa\[15..12\]" "" } { 584 328 392 600 "xa\[15\]" "" } { 664 328 392 680 "xa\[13\]" "" } { 704 328 392 720 "xa\[12\]" "" } { 632 336 496 648 "xa\[14\]" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "xa\[13\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "xa\[15\] " "Info: Assuming node \"xa\[15\]\" is an undefined clock" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 464 144 312 480 "xa\[15..12\]" "" } { 584 328 392 600 "xa\[15\]" "" } { 664 328 392 680 "xa\[13\]" "" } { 704 328 392 720 "xa\[12\]" "" } { 632 336 496 648 "xa\[14\]" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "xa\[15\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "xa\[14\] " "Info: Assuming node \"xa\[14\]\" is an undefined clock" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 464 144 312 480 "xa\[15..12\]" "" } { 584 328 392 600 "xa\[15\]" "" } { 664 328 392 680 "xa\[13\]" "" } { 704 328 392 720 "xa\[12\]" "" } { 632 336 496 648 "xa\[14\]" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "xa\[14\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "xwe " "Info: Assuming node \"xwe\" is an undefined clock" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 552 144 312 568 "xwe" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "xwe" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "xd\[8\] " "Info: Assuming node \"xd\[8\]\" is an undefined clock" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 336 152 320 352 "xd\[15..13\]" "" } { 296 152 320 312 "xd\[12..8\]" "" } { 256 152 320 272 "xd\[7..0\]" "" } { 336 352 392 352 "xd\[8\]" "" } { 352 352 392 368 "xd\[9\]" "" } { 368 352 392 384 "xd\[10\]" "" } { 384 352 392 400 "xd\[11\]" "" } { 400 352 392 416 "xd\[12\]" "" } { 416 352 392 432 "xd\[13\]" "" } { 432 352 392 448 "xd\[14\]" "" } { 448 352 392 464 "xd\[15\]" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "xd\[8\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "xd\[9\] " "Info: Assuming node \"xd\[9\]\" is an undefined clock" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 336 152 320 352 "xd\[15..13\]" "" } { 296 152 320 312 "xd\[12..8\]" "" } { 256 152 320 272 "xd\[7..0\]" "" } { 336 352 392 352 "xd\[8\]" "" } { 352 352 392 368 "xd\[9\]" "" } { 368 352 392 384 "xd\[10\]" "" } { 384 352 392 400 "xd\[11\]" "" } { 400 352 392 416 "xd\[12\]" "" } { 416 352 392 432 "xd\[13\]" "" } { 432 352 392 448 "xd\[14\]" "" } { 448 352 392 464 "xd\[15\]" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "xd\[9\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "xd\[12\] " "Info: Assuming node \"xd\[12\]\" is an undefined clock" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 336 152 320 352 "xd\[15..13\]" "" } { 296 152 320 312 "xd\[12..8\]" "" } { 256 152 320 272 "xd\[7..0\]" "" } { 336 352 392 352 "xd\[8\]" "" } { 352 352 392 368 "xd\[9\]" "" } { 368 352 392 384 "xd\[10\]" "" } { 384 352 392 400 "xd\[11\]" "" } { 400 352 392 416 "xd\[12\]" "" } { 416 352 392 432 "xd\[13\]" "" } { 432 352 392 448 "xd\[14\]" "" } { 448 352 392 464 "xd\[15\]" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "xd\[12\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "xd\[10\] " "Info: Assuming node \"xd\[10\]\" is an undefined clock" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 336 152 320 352 "xd\[15..13\]" "" } { 296 152 320 312 "xd\[12..8\]" "" } { 256 152 320 272 "xd\[7..0\]" "" } { 336 352 392 352 "xd\[8\]" "" } { 352 352 392 368 "xd\[9\]" "" } { 368 352 392 384 "xd\[10\]" "" } { 384 352 392 400 "xd\[11\]" "" } { 400 352 392 416 "xd\[12\]" "" } { 416 352 392 432 "xd\[13\]" "" } { 432 352 392 448 "xd\[14\]" "" } { 448 352 392 464 "xd\[15\]" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "xd\[10\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "xd\[11\] " "Info: Assuming node \"xd\[11\]\" is an undefined clock" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 336 152 320 352 "xd\[15..13\]" "" } { 296 152 320 312 "xd\[12..8\]" "" } { 256 152 320 272 "xd\[7..0\]" "" } { 336 352 392 352 "xd\[8\]" "" } { 352 352 392 368 "xd\[9\]" "" } { 368 352 392 384 "xd\[10\]" "" } { 384 352 392 400 "xd\[11\]" "" } { 400 352 392 416 "xd\[12\]" "" } { 416 352 392 432 "xd\[13\]" "" } { 432 352 392 448 "xd\[14\]" "" } { 448 352 392 464 "xd\[15\]" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "xd\[11\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "10 " "Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "inst16~29 " "Info: Detected gated clock \"inst16~29\" as buffer" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 536 608 656 600 "inst16" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "inst16~29" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst16 " "Info: Detected gated clock \"inst16\" as buffer" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 536 608 656 600 "inst16" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "inst16" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "state:inst2\|clear " "Info: Detected ripple clock \"state:inst2\|clear\" as buffer" {  } { { "state/state.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/state/state.vhd" 17 -1 0 } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "state:inst2\|clear" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "74373:inst3\|16 " "Info: Detected gated clock \"74373:inst3\|16\" as buffer" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 480 232 296 560 "16" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "74373:inst3\|16" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "74373:inst3\|13 " "Info: Detected gated clock \"74373:inst3\|13\" as buffer" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 216 232 296 296 "13" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "74373:inst3\|13" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "74373:inst3\|12 " "Info: Detected gated clock \"74373:inst3\|12\" as buffer" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 128 232 296 208 "12" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "74373:inst3\|12" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "74373:inst3\|15 " "Info: Detected gated clock \"74373:inst3\|15\" as buffer" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 392 232 296 472 "15" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "74373:inst3\|15" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "74373:inst3\|14 " "Info: Detected gated clock \"74373:inst3\|14\" as buffer" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 304 232 296 384 "14" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "74373:inst3\|14" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst14~37 " "Info: Detected gated clock \"inst14~37\" as buffer" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 536 920 984 584 "inst14" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "inst14~37" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "freq:inst\|Q " "Info: Detected ripple clock \"freq:inst\|Q\" as buffer" {  } { { "freq/freq.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/freq/freq.vhd" 18 -1 0 } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "freq:inst\|Q" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}