lcd.map.qmsg

这是一个用VHDL +图形法在CPLD内部搭建的液晶显示的驱动程序。液晶是ocmj5*10系列

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dd dd:inst10 " "Info: Elaborating entity \"dd\" for hierarchy \"dd:inst10\"" {  } { { "lcd.bdf" "inst10" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 256 1256 1352 352 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74373 " "Info: Found entity 1: 74373" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74373 74373:inst3 " "Info: Elaborating entity \"74373\" for hierarchy \"74373:inst3\"" {  } { { "lcd.bdf" "inst3" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 328 392 512 520 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram ram:inst1 " "Info: Elaborating entity \"ram\" for hierarchy \"ram:inst1\"" {  } { { "lcd.bdf" "inst1" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 200 640 856 328 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51sp1/libraries/others/maxplus2/74373b.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51sp1/libraries/others/maxplus2/74373b.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74373b " "Info: Found entity 1: 74373b" {  } { { "74373b.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373b.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74373b 74373b:inst4 " "Info: Elaborating entity \"74373b\" for hierarchy \"74373b:inst4\"" {  } { { "lcd.bdf" "inst4" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 224 384 520 304 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373b:inst4\|74 " "Warning: Converting TRI node \"74373b:inst4\|74\" that feeds logic to a wire" {  } { { "74373b.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373b.bdf" { { 744 352 400 776 "74" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373b:inst4\|73 " "Warning: Converting TRI node \"74373b:inst4\|73\" that feeds logic to a wire" {  } { { "74373b.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373b.bdf" { { 656 352 400 688 "73" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373b:inst4\|72 " "Warning: Converting TRI node \"74373b:inst4\|72\" that feeds logic to a wire" {  } { { "74373b.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373b.bdf" { { 568 352 400 600 "72" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373b:inst4\|71 " "Warning: Converting TRI node \"74373b:inst4\|71\" that feeds logic to a wire" {  } { { "74373b.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373b.bdf" { { 480 352 400 512 "71" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373b:inst4\|70 " "Warning: Converting TRI node \"74373b:inst4\|70\" that feeds logic to a wire" {  } { { "74373b.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373b.bdf" { { 392 352 400 424 "70" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373b:inst4\|69 " "Warning: Converting TRI node \"74373b:inst4\|69\" that feeds logic to a wire" {  } { { "74373b.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373b.bdf" { { 304 352 400 336 "69" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373b:inst4\|68 " "Warning: Converting TRI node \"74373b:inst4\|68\" that feeds logic to a wire" {  } { { "74373b.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373b.bdf" { { 216 352 400 248 "68" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373b:inst4\|67 " "Warning: Converting TRI node \"74373b:inst4\|67\" that feeds logic to a wire" {  } { { "74373b.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373b.bdf" { { 128 352 400 160 "67" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373:inst3\|74 " "Warning: Converting TRI node \"74373:inst3\|74\" that feeds logic to a wire" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 760 320 368 792 "74" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373:inst3\|73 " "Warning: Converting TRI node \"74373:inst3\|73\" that feeds logic to a wire" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 672 320 368 704 "73" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373:inst3\|72 " "Warning: Converting TRI node \"74373:inst3\|72\" that feeds logic to a wire" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 584 320 368 616 "72" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373:inst3\|71 " "Warning: Converting TRI node \"74373:inst3\|71\" that feeds logic to a wire" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 496 320 368 528 "71" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373:inst3\|70 " "Warning: Converting TRI node \"74373:inst3\|70\" that feeds logic to a wire" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 408 320 368 440 "70" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373:inst3\|69 " "Warning: Converting TRI node \"74373:inst3\|69\" that feeds logic to a wire" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 320 320 368 352 "69" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373:inst3\|68 " "Warning: Converting TRI node \"74373:inst3\|68\" that feeds logic to a wire" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 232 320 368 264 "68" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74373:inst3\|67 " "Warning: Converting TRI node \"74373:inst3\|67\" that feeds logic to a wire" {  } { { "74373.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/74373.bdf" { { 144 320 368 176 "67" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "state:inst2\|write state:inst2\|req " "Info: Duplicate register \"state:inst2\|write\" merged to single register \"state:inst2\|req\"" {  } { { "state/state.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/state/state.vhd" 28 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|lcd\|state:inst2\|next_state 11 " "Info: State machine \"\|lcd\|state:inst2\|next_state\" contains 11 states" {  } { { "state/state.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/state/state.vhd" 24 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}