lcd.map.qmsg

这是一个用VHDL +图形法在CPLD内部搭建的液晶显示的驱动程序。液晶是ocmj5*10系列

{ "Info" "ISGN_START_ELABORATION_TOP" "lcd " "Info: Elaborating entity \"lcd\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_PIN_IGNORED" "empty " "Warning: Pin \"empty\" not connected" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 720 112 280 736 "empty\[81..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" not connected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "state state:inst2 " "Info: Elaborating entity \"state\" for hierarchy \"state:inst2\"" {  } { { "lcd.bdf" "inst2" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 152 1008 1192 312 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "next_state state.vhd(214) " "Warning (10492): VHDL Process Statement warning at state.vhd(214): signal \"next_state\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "state/state.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/state/state.vhd" 214 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "freq freq:inst " "Info: Elaborating entity \"freq\" for hierarchy \"freq:inst\"" {  } { { "lcd.bdf" "inst" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 64 600 696 160 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Q freq.vhd(27) " "Warning (10492): VHDL Process Statement warning at freq.vhd(27): signal \"Q\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "freq/freq.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/freq/freq.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "try try:inst9 " "Info: Elaborating entity \"try\" for hierarchy \"try:inst9\"" {  } { { "lcd.bdf" "inst9" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 392 736 912 488 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51sp1/libraries/others/maxplus2/DFF2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51sp1/libraries/others/maxplus2/DFF2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DFF2 " "Info: Found entity 1: DFF2" {  } { { "DFF2.bdf" "" { Schematic "c:/altera/quartus51sp1/libraries/others/maxplus2/DFF2.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DFF2 try:inst9\|DFF2:inst " "Info: Elaborating entity \"DFF2\" for hierarchy \"try:inst9\|DFF2:inst\"" {  } { { "dready/try.bdf" "inst" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/dready/try.bdf" { { 152 392 496 248 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}