lcd.hier_info

这是一个用VHDL +图形法在CPLD内部搭建的液晶显示的驱动程序。液晶是ocmj5*10系列

|lcd
req <= state:inst2.req
clk => freq:inst.clk
clk => state:inst2.clk1
clk => ram:inst1.clk
xwe => inst11.IN0
xd[0] => 74373b:inst4.D[1]
xd[1] => 74373b:inst4.D[2]
xd[2] => 74373b:inst4.D[3]
xd[3] => 74373b:inst4.D[4]
xd[4] => 74373b:inst4.D[5]
xd[5] => 74373b:inst4.D[6]
xd[6] => 74373b:inst4.D[7]
xd[7] => 74373b:inst4.D[8]
xd[8] => 74373:inst3.D1
xd[9] => 74373:inst3.D2
xd[10] => 74373:inst3.D3
xd[11] => 74373:inst3.D4
xd[12] => 74373:inst3.D5
xd[13] => 74373:inst3.D6
xd[14] => 74373:inst3.D7
xd[15] => 74373:inst3.D8
xa[12] => insist14.IN0
xa[13] => inst13.IN0
xa[14] => inst15.IN1
xa[15] => inst12.IN0
lcd_busy => state:inst2.busy
ready <= try:inst9.ready
data_out[0] <= state:inst2.data_out[0]
data_out[1] <= state:inst2.data_out[1]
data_out[2] <= state:inst2.data_out[2]
data_out[3] <= state:inst2.data_out[3]
data_out[4] <= state:inst2.data_out[4]
data_out[5] <= state:inst2.data_out[5]
data_out[6] <= state:inst2.data_out[6]
data_out[7] <= state:inst2.data_out[7]
empty[0] => ~NO_FANOUT~
empty[1] => ~NO_FANOUT~
empty[2] => ~NO_FANOUT~
empty[3] => ~NO_FANOUT~
empty[4] => ~NO_FANOUT~
empty[5] => ~NO_FANOUT~
empty[6] => ~NO_FANOUT~
empty[7] => ~NO_FANOUT~
empty[8] => ~NO_FANOUT~
empty[9] => ~NO_FANOUT~
empty[10] => ~NO_FANOUT~
empty[11] => ~NO_FANOUT~
empty[12] => ~NO_FANOUT~
empty[13] => ~NO_FANOUT~
empty[14] => ~NO_FANOUT~
empty[15] => ~NO_FANOUT~
empty[16] => ~NO_FANOUT~
empty[17] => ~NO_FANOUT~
empty[18] => ~NO_FANOUT~
empty[19] => ~NO_FANOUT~
empty[20] => ~NO_FANOUT~
empty[21] => ~NO_FANOUT~
empty[22] => ~NO_FANOUT~
empty[23] => ~NO_FANOUT~
empty[24] => ~NO_FANOUT~
empty[25] => ~NO_FANOUT~
empty[26] => ~NO_FANOUT~
empty[27] => ~NO_FANOUT~
empty[28] => ~NO_FANOUT~
empty[29] => ~NO_FANOUT~
empty[30] => ~NO_FANOUT~
empty[31] => ~NO_FANOUT~
empty[32] => ~NO_FANOUT~
empty[33] => ~NO_FANOUT~
empty[34] => ~NO_FANOUT~
empty[35] => ~NO_FANOUT~
empty[36] => ~NO_FANOUT~
empty[37] => ~NO_FANOUT~
empty[38] => ~NO_FANOUT~
empty[39] => ~NO_FANOUT~
empty[40] => ~NO_FANOUT~
empty[41] => ~NO_FANOUT~
empty[42] => ~NO_FANOUT~
empty[43] => ~NO_FANOUT~
empty[44] => ~NO_FANOUT~
empty[45] => ~NO_FANOUT~
empty[46] => ~NO_FANOUT~
empty[47] => ~NO_FANOUT~
empty[48] => ~NO_FANOUT~
empty[49] => ~NO_FANOUT~
empty[50] => ~NO_FANOUT~
empty[51] => ~NO_FANOUT~
empty[52] => ~NO_FANOUT~
empty[53] => ~NO_FANOUT~
empty[54] => ~NO_FANOUT~
empty[55] => ~NO_FANOUT~
empty[56] => ~NO_FANOUT~
empty[57] => ~NO_FANOUT~
empty[58] => ~NO_FANOUT~
empty[59] => ~NO_FANOUT~
empty[60] => ~NO_FANOUT~
empty[61] => ~NO_FANOUT~
empty[62] => ~NO_FANOUT~
empty[63] => ~NO_FANOUT~
empty[64] => ~NO_FANOUT~
empty[65] => ~NO_FANOUT~
empty[66] => ~NO_FANOUT~
empty[67] => ~NO_FANOUT~
empty[68] => ~NO_FANOUT~
empty[69] => ~NO_FANOUT~
empty[70] => ~NO_FANOUT~
empty[71] => ~NO_FANOUT~
empty[72] => ~NO_FANOUT~
empty[73] => ~NO_FANOUT~
empty[74] => ~NO_FANOUT~
empty[75] => ~NO_FANOUT~
empty[76] => ~NO_FANOUT~
empty[77] => ~NO_FANOUT~
empty[78] => ~NO_FANOUT~
empty[79] => ~NO_FANOUT~
empty[80] => ~NO_FANOUT~
empty[81] => ~NO_FANOUT~


|lcd|state:inst2
clk => state_out[3]~reg0.CLK
clk => state_out[2]~reg0.CLK
clk => state_out[1]~reg0.CLK
clk => state_out[0]~reg0.CLK
clk => data_out[7]~reg0.CLK
clk => data_out[6]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => req~reg0.CLK
clk => write.CLK
clk => i[31].CLK
clk => i[30].CLK
clk => i[29].CLK
clk => i[28].CLK
clk => i[27].CLK
clk => i[26].CLK
clk => i[25].CLK
clk => i[24].CLK
clk => i[23].CLK
clk => i[22].CLK
clk => i[21].CLK
clk => i[20].CLK
clk => i[19].CLK
clk => i[18].CLK
clk => i[17].CLK
clk => i[16].CLK
clk => i[15].CLK
clk => i[14].CLK
clk => i[13].CLK
clk => i[12].CLK
clk => i[11].CLK
clk => i[10].CLK
clk => i[9].CLK
clk => i[8].CLK
clk => i[7].CLK
clk => i[6].CLK
clk => i[5].CLK
clk => i[4].CLK
clk => i[3].CLK
clk => i[2].CLK
clk => i[1].CLK
clk => i[0].CLK
clk => write_out~reg0.CLK
clk => clear1.CLK
clk => next_state~15.IN1
clk1 => clear~reg0.CLK
flag => next_state~4.OUTPUTSELECT
flag => next_state~5.OUTPUTSELECT
flag => next_state~6.OUTPUTSELECT
flag => next_state~7.OUTPUTSELECT
flag => next_state~8.OUTPUTSELECT
flag => next_state~9.OUTPUTSELECT
flag => next_state~10.OUTPUTSELECT
flag => next_state~11.OUTPUTSELECT
flag => next_state~12.OUTPUTSELECT
flag => next_state~13.OUTPUTSELECT
flag => next_state~14.OUTPUTSELECT
flag => state_out[3]~reg0.ENA
flag => state_out[2]~reg0.ENA
flag => state_out[1]~reg0.ENA
flag => state_out[0]~reg0.ENA
flag => data_out[7]~reg0.ENA
flag => data_out[6]~reg0.ENA
flag => data_out[5]~reg0.ENA
flag => data_out[4]~reg0.ENA
flag => data_out[3]~reg0.ENA
flag => data_out[2]~reg0.ENA
flag => data_out[1]~reg0.ENA
flag => data_out[0]~reg0.ENA
flag => req~reg0.ENA
flag => write.ENA
flag => i[31].ENA
flag => i[30].ENA
flag => i[29].ENA
flag => i[28].ENA
flag => i[27].ENA
flag => i[26].ENA
flag => i[25].ENA
flag => i[24].ENA
flag => i[23].ENA
flag => i[22].ENA
flag => i[21].ENA
flag => i[20].ENA
flag => i[19].ENA
flag => i[18].ENA
flag => i[17].ENA
flag => i[16].ENA
flag => i[15].ENA
flag => i[14].ENA
flag => i[13].ENA
flag => i[12].ENA
flag => i[11].ENA
flag => i[10].ENA
flag => i[9].ENA
flag => i[8].ENA
flag => i[7].ENA
flag => i[6].ENA
flag => i[5].ENA
flag => i[4].ENA
flag => i[3].ENA
flag => i[2].ENA
flag => i[1].ENA
flag => i[0].ENA
flag => write_out~reg0.ENA
flag => clear1.ENA
busy => process0~2.IN1
busy => process0~1.IN1
row[0] => data_out~18.DATAB
row[0] => data_out~37.DATAB
row[1] => data_out~17.DATAB
row[1] => data_out~36.DATAB
row[2] => data_out~16.DATAB
row[2] => data_out~35.DATAB
data_in[0] => LessThan~0.IN16
data_in[0] => LessThan~1.IN16
data_in[0] => LessThan~2.IN16
data_in[0] => data_out~28.DATAB
data_in[1] => LessThan~0.IN15
data_in[1] => LessThan~1.IN15
data_in[1] => LessThan~2.IN15
data_in[1] => data_out~27.DATAB
data_in[2] => LessThan~0.IN14
data_in[2] => LessThan~1.IN14
data_in[2] => LessThan~2.IN14
data_in[2] => data_out~26.DATAB
data_in[3] => LessThan~0.IN13
data_in[3] => LessThan~1.IN13
data_in[3] => LessThan~2.IN13
data_in[3] => data_out~25.DATAB
data_in[4] => LessThan~0.IN12
data_in[4] => LessThan~1.IN12
data_in[4] => LessThan~2.IN12
data_in[4] => data_out~24.DATAB
data_in[5] => LessThan~0.IN11
data_in[5] => LessThan~1.IN11
data_in[5] => LessThan~2.IN11
data_in[5] => data_out~23.DATAB
data_in[5] => add~2.IN6
data_in[6] => LessThan~0.IN10
data_in[6] => LessThan~1.IN10
data_in[6] => LessThan~2.IN10
data_in[6] => data_out~22.DATAB
data_in[6] => add~2.IN5
data_in[7] => LessThan~0.IN9
data_in[7] => LessThan~1.IN9
data_in[7] => LessThan~2.IN9
data_in[7] => data_out~21.DATAB
data_in[7] => add~2.IN4
req <= req~reg0.DB_MAX_OUTPUT_PORT_TYPE
read_add[0] <= i[0].DB_MAX_OUTPUT_PORT_TYPE
read_add[1] <= i[1].DB_MAX_OUTPUT_PORT_TYPE
read_add[2] <= i[2].DB_MAX_OUTPUT_PORT_TYPE
read_add[3] <= i[3].DB_MAX_OUTPUT_PORT_TYPE
read_add[4] <= i[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
clear <= clear~reg0.DB_MAX_OUTPUT_PORT_TYPE
write_out <= write_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
state_out[0] <= state_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
state_out[1] <= state_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
state_out[2] <= state_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
state_out[3] <= state_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|lcd|freq:inst
clk => i[8].CLK
clk => i[7].CLK
clk => i[6].CLK
clk => i[5].CLK
clk => i[4].CLK
clk => i[3].CLK
clk => i[2].CLK
clk => i[1].CLK
clk => i[0].CLK
clk => Q.CLK
clk_out <= Q.DB_MAX_OUTPUT_PORT_TYPE


|lcd|try:inst9
ready <= DFF2:inst.QN
we => inst12.IN0
write_add[0] => inst10.IN1
write_add[1] => inst10.IN2
write_add[2] => inst8.IN0
write_add[3] => inst9.IN0
write_add[4] => inst10.IN4
clear => DFF2:inst.CLRN
flag <= DFF2:inst.Q


|lcd|try:inst9|DFF2:inst
Q <= 3.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 3.ACLR
CLK => 3.CLK
D => 3.DATAIN
PRN => 3.PRESET
QN <= 6.DB_MAX_OUTPUT_PORT_TYPE


|lcd|dd:inst10
s0 => s1~reg0.DATAIN
s0 => s1~reg0.CLK
wr => s1~reg0.ACLR
s1 <= s1~reg0.DB_MAX_OUTPUT_PORT_TYPE


|lcd|74373:inst3
Q8 <= 74.DB_MAX_OUTPUT_PORT_TYPE
D8 => 19.DATAIN
G => 19.LATCH_ENABLE
G => 18.LATCH_ENABLE
G => 17.LATCH_ENABLE
G => 16.LATCH_ENABLE
G => 15.LATCH_ENABLE
G => 14.LATCH_ENABLE
G => 13.LATCH_ENABLE
G => 12.LATCH_ENABLE
OEN => 1.IN0
Q7 <= 73.DB_MAX_OUTPUT_PORT_TYPE
D7 => 18.DATAIN
Q6 <= 72.DB_MAX_OUTPUT_PORT_TYPE
D6 => 17.DATAIN
Q5 <= 71.DB_MAX_OUTPUT_PORT_TYPE
D5 => 16.DATAIN
Q4 <= 70.DB_MAX_OUTPUT_PORT_TYPE
D4 => 15.DATAIN
Q3 <= 69.DB_MAX_OUTPUT_PORT_TYPE
D3 => 14.DATAIN
Q2 <= 68.DB_MAX_OUTPUT_PORT_TYPE
D2 => 13.DATAIN
Q1 <= 67.DB_MAX_OUTPUT_PORT_TYPE
D1 => 12.DATAIN


|lcd|ram:inst1
clk => data_out[7]~reg0.CLK
clk => data_out[6]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => ram_block.CLK0
data_in[0] => ram_block.DATAIN
data_in[1] => ram_block.DATAIN1
data_in[2] => ram_block.DATAIN2
data_in[3] => ram_block.DATAIN3
data_in[4] => ram_block.DATAIN4
data_in[5] => ram_block.DATAIN5
data_in[6] => ram_block.DATAIN6
data_in[7] => ram_block.DATAIN7
write_address[0] => ram_block.WADDR
write_address[1] => ram_block.WADDR1
write_address[2] => ram_block.WADDR2
write_address[3] => ram_block.WADDR3
write_address[4] => ram_block.WADDR4
read_address[0] => ram_block.RADDR
read_address[1] => ram_block.RADDR1
read_address[2] => ram_block.RADDR2
read_address[3] => ram_block.RADDR3
read_address[4] => ram_block.RADDR4
we => ram_block.WE
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|lcd|74373b:inst4
Q8 <= 74.DB_MAX_OUTPUT_PORT_TYPE
D8 => 19.DATAIN
G => 19.LATCH_ENABLE
G => 18.LATCH_ENABLE
G => 17.LATCH_ENABLE
G => 16.LATCH_ENABLE
G => 15.LATCH_ENABLE
G => 14.LATCH_ENABLE
G => 13.LATCH_ENABLE
G => 12.LATCH_ENABLE
OEN => 1.IN0
Q7 <= 73.DB_MAX_OUTPUT_PORT_TYPE
D7 => 18.DATAIN
Q6 <= 72.DB_MAX_OUTPUT_PORT_TYPE
D6 => 17.DATAIN
Q5 <= 71.DB_MAX_OUTPUT_PORT_TYPE
D5 => 16.DATAIN
Q4 <= 70.DB_MAX_OUTPUT_PORT_TYPE
D4 => 15.DATAIN
Q3 <= 69.DB_MAX_OUTPUT_PORT_TYPE
D3 => 14.DATAIN
Q2 <= 68.DB_MAX_OUTPUT_PORT_TYPE
D2 => 13.DATAIN
Q1 <= 67.DB_MAX_OUTPUT_PORT_TYPE
D1 => 12.DATAIN