lcd.fit.qmsg

这是一个用VHDL +图形法在CPLD内部搭建的液晶显示的驱动程序。液晶是ocmj5*10系列

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition " "Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 10 15:35:41 2007 " "Info: Processing started: Tue Jul 10 15:35:41 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off lcd -c lcd " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lcd -c lcd" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "lcd EPM1270T144C5 " "Info: Selected device EPM1270T144C5 for design \"lcd\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Info: Device EPM570T144C5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Info: Device EPM570T144I5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Info: Device EPM1270T144I5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144C5ES " "Info: Device EPM1270T144C5ES is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "4 115 " "Info: No exact pin location assignment(s) for 4 pins of 115 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "empty\[3\] " "Info: Pin empty\[3\] not assigned to an exact location on the device" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 720 112 280 736 "empty\[81..0\]" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "empty\[3\]" } } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "" { empty[3] } "NODE_NAME" } "" } } { "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.fld" "" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.fld" "" "" { empty[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "empty\[2\] " "Info: Pin empty\[2\] not assigned to an exact location on the device" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 720 112 280 736 "empty\[81..0\]" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "empty\[2\]" } } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "" { empty[2] } "NODE_NAME" } "" } } { "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.fld" "" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.fld" "" "" { empty[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "empty\[1\] " "Info: Pin empty\[1\] not assigned to an exact location on the device" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 720 112 280 736 "empty\[81..0\]" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "empty\[1\]" } } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "" { empty[1] } "NODE_NAME" } "" } } { "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.fld" "" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.fld" "" "" { empty[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "empty\[0\] " "Info: Pin empty\[0\] not assigned to an exact location on the device" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 720 112 280 736 "empty\[81..0\]" "" } } } } { "c:/altera/quartus51sp1/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51sp1/bin/Assignment Editor.qase" 1 { { 0 "empty\[0\]" } } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "lcd" "UNKNOWN" "V1" "D:/study/d_dsp/two lcd in altera/lcd_restored/db/lcd.quartus_db" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/" "" "" { empty[0] } "NODE_NAME" } "" } } { "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.fld" "" { Floorplan "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.fld" "" "" { empty[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 18 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 18" {  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 104 152 320 120 "clk" "" } { 184 992 1008 200 "clk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "freq:inst\|Q Global clock " "Info: Automatically promoted some destinations of signal \"freq:inst\|Q\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "freq:inst\|Q " "Info: Destination \"freq:inst\|Q\" may be non-global or may not use global clock" {  } { { "freq/freq.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/freq/freq.vhd" 18 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "freq/freq.vhd" "" { Text "D:/study/d_dsp/two lcd in altera/lcd_restored/freq/freq.vhd" 18 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "inst16 Global clock " "Info: Automatically promoted some destinations of signal \"inst16\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rtl~16 " "Info: Destination \"rtl~16\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rtl~17 " "Info: Destination \"rtl~17\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rtl~18 " "Info: Destination \"rtl~18\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rtl~19 " "Info: Destination \"rtl~19\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rtl~20 " "Info: Destination \"rtl~20\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rtl~21 " "Info: Destination \"rtl~21\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rtl~22 " "Info: Destination \"rtl~22\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rtl~23 " "Info: Destination \"rtl~23\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rtl~24 " "Info: Destination \"rtl~24\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rtl~25 " "Info: Destination \"rtl~25\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "lcd.bdf" "" { Schematic "D:/study/d_dsp/two lcd in altera/lcd_restored/lcd.bdf" { { 536 608 656 600 "inst16" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0 0 "Moving registers into LUTs to improve timing and density" 0 0}