📄 lcd.tan.rpt
字号:
; N/A ; 90.08 MHz ( period = 11.101 ns ) ; state:inst2|i[9] ; state:inst2|i[6] ; clk ; clk ; None ; None ; 10.392 ns ;
; N/A ; 90.14 MHz ( period = 11.094 ns ) ; state:inst2|i[0] ; state:inst2|i[25] ; clk ; clk ; None ; None ; 10.385 ns ;
; N/A ; 90.14 MHz ( period = 11.094 ns ) ; state:inst2|i[0] ; state:inst2|i[24] ; clk ; clk ; None ; None ; 10.385 ns ;
; N/A ; 90.14 MHz ( period = 11.094 ns ) ; state:inst2|i[0] ; state:inst2|i[23] ; clk ; clk ; None ; None ; 10.385 ns ;
; N/A ; 90.14 MHz ( period = 11.094 ns ) ; state:inst2|i[0] ; state:inst2|i[22] ; clk ; clk ; None ; None ; 10.385 ns ;
; N/A ; 90.14 MHz ( period = 11.094 ns ) ; state:inst2|i[0] ; state:inst2|i[21] ; clk ; clk ; None ; None ; 10.385 ns ;
; N/A ; 90.14 MHz ( period = 11.094 ns ) ; state:inst2|i[0] ; state:inst2|i[20] ; clk ; clk ; None ; None ; 10.385 ns ;
; N/A ; 90.14 MHz ( period = 11.094 ns ) ; state:inst2|i[0] ; state:inst2|i[19] ; clk ; clk ; None ; None ; 10.385 ns ;
; N/A ; 90.14 MHz ( period = 11.094 ns ) ; state:inst2|i[0] ; state:inst2|i[18] ; clk ; clk ; None ; None ; 10.385 ns ;
; N/A ; 90.14 MHz ( period = 11.094 ns ) ; state:inst2|i[0] ; state:inst2|i[17] ; clk ; clk ; None ; None ; 10.385 ns ;
; N/A ; 90.14 MHz ( period = 11.094 ns ) ; state:inst2|i[0] ; state:inst2|i[16] ; clk ; clk ; None ; None ; 10.385 ns ;
; N/A ; 90.25 MHz ( period = 11.080 ns ) ; state:inst2|i[14] ; state:inst2|i[1] ; clk ; clk ; None ; None ; 10.371 ns ;
; N/A ; 90.25 MHz ( period = 11.080 ns ) ; state:inst2|i[14] ; state:inst2|i[2] ; clk ; clk ; None ; None ; 10.371 ns ;
; N/A ; 90.25 MHz ( period = 11.080 ns ) ; state:inst2|i[14] ; state:inst2|i[0] ; clk ; clk ; None ; None ; 10.371 ns ;
; N/A ; 90.25 MHz ( period = 11.080 ns ) ; state:inst2|i[14] ; state:inst2|i[3] ; clk ; clk ; None ; None ; 10.371 ns ;
; N/A ; 90.25 MHz ( period = 11.080 ns ) ; state:inst2|i[14] ; state:inst2|i[5] ; clk ; clk ; None ; None ; 10.371 ns ;
; N/A ; 90.25 MHz ( period = 11.080 ns ) ; state:inst2|i[14] ; state:inst2|i[4] ; clk ; clk ; None ; None ; 10.371 ns ;
; N/A ; 90.37 MHz ( period = 11.066 ns ) ; state:inst2|i[1] ; state:inst2|i[15] ; clk ; clk ; None ; None ; 10.357 ns ;
; N/A ; 90.37 MHz ( period = 11.066 ns ) ; state:inst2|i[1] ; state:inst2|i[14] ; clk ; clk ; None ; None ; 10.357 ns ;
; N/A ; 90.37 MHz ( period = 11.066 ns ) ; state:inst2|i[1] ; state:inst2|i[13] ; clk ; clk ; None ; None ; 10.357 ns ;
; N/A ; 90.37 MHz ( period = 11.066 ns ) ; state:inst2|i[1] ; state:inst2|i[12] ; clk ; clk ; None ; None ; 10.357 ns ;
; N/A ; 90.37 MHz ( period = 11.066 ns ) ; state:inst2|i[1] ; state:inst2|i[11] ; clk ; clk ; None ; None ; 10.357 ns ;
; N/A ; 90.37 MHz ( period = 11.066 ns ) ; state:inst2|i[1] ; state:inst2|i[10] ; clk ; clk ; None ; None ; 10.357 ns ;
; N/A ; 90.37 MHz ( period = 11.066 ns ) ; state:inst2|i[1] ; state:inst2|i[9] ; clk ; clk ; None ; None ; 10.357 ns ;
; N/A ; 90.37 MHz ( period = 11.066 ns ) ; state:inst2|i[1] ; state:inst2|i[8] ; clk ; clk ; None ; None ; 10.357 ns ;
; N/A ; 90.37 MHz ( period = 11.066 ns ) ; state:inst2|i[1] ; state:inst2|i[7] ; clk ; clk ; None ; None ; 10.357 ns ;
; N/A ; 90.37 MHz ( period = 11.066 ns ) ; state:inst2|i[1] ; state:inst2|i[6] ; clk ; clk ; None ; None ; 10.357 ns ;
; N/A ; 90.96 MHz ( period = 10.994 ns ) ; ram:inst1|ram_block~300 ; ram:inst1|data_out[2] ; clk ; clk ; None ; None ; 10.285 ns ;
; N/A ; 91.10 MHz ( period = 10.977 ns ) ; state:inst2|i[11] ; state:inst2|i[15] ; clk ; clk ; None ; None ; 10.268 ns ;
; N/A ; 91.10 MHz ( period = 10.977 ns ) ; state:inst2|i[11] ; state:inst2|i[14] ; clk ; clk ; None ; None ; 10.268 ns ;
; N/A ; 91.10 MHz ( period = 10.977 ns ) ; state:inst2|i[11] ; state:inst2|i[13] ; clk ; clk ; None ; None ; 10.268 ns ;
; N/A ; 91.10 MHz ( period = 10.977 ns ) ; state:inst2|i[11] ; state:inst2|i[12] ; clk ; clk ; None ; None ; 10.268 ns ;
; N/A ; 91.10 MHz ( period = 10.977 ns ) ; state:inst2|i[11] ; state:inst2|i[11] ; clk ; clk ; None ; None ; 10.268 ns ;
; N/A ; 91.10 MHz ( period = 10.977 ns ) ; state:inst2|i[11] ; state:inst2|i[10] ; clk ; clk ; None ; None ; 10.268 ns ;
; N/A ; 91.10 MHz ( period = 10.977 ns ) ; state:inst2|i[11] ; state:inst2|i[9] ; clk ; clk ; None ; None ; 10.268 ns ;
; N/A ; 91.10 MHz ( period = 10.977 ns ) ; state:inst2|i[11] ; state:inst2|i[8] ; clk ; clk ; None ; None ; 10.268 ns ;
; N/A ; 91.10 MHz ( period = 10.977 ns ) ; state:inst2|i[11] ; state:inst2|i[7] ; clk ; clk ; None ; None ; 10.268 ns ;
; N/A ; 91.10 MHz ( period = 10.977 ns ) ; state:inst2|i[11] ; state:inst2|i[6] ; clk ; clk ; None ; None ; 10.268 ns ;
; N/A ; 91.11 MHz ( period = 10.976 ns ) ; state:inst2|i[8] ; state:inst2|i[1] ; clk ; clk ; None ; None ; 10.267 ns ;
; N/A ; 91.11 MHz ( period = 10.976 ns ) ; state:inst2|i[8] ; state:inst2|i[2] ; clk ; clk ; None ; None ; 10.267 ns ;
; N/A ; 91.11 MHz ( period = 10.976 ns ) ; state:inst2|i[8] ; state:inst2|i[0] ; clk ; clk ; None ; None ; 10.267 ns ;
; N/A ; 91.11 MHz ( period = 10.976 ns ) ; state:inst2|i[8] ; state:inst2|i[3] ; clk ; clk ; None ; None ; 10.267 ns ;
; N/A ; 91.11 MHz ( period = 10.976 ns ) ; state:inst2|i[8] ; state:inst2|i[5] ; clk ; clk ; None ; None ; 10.267 ns ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
+-----------------------------------------+-----------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clk' ;
+------------------------------------------+-----------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+-----------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; ram:inst1|data_out[7] ; state:inst2|next_state.s9 ; clk ; clk ; None ; None ; 3.160 ns ;
; Not operational: Clock Skew > Data Delay ; state:inst2|clear ; dd:inst10|s1 ; clk ; clk ; None ; None ; 1.245 ns ;
; Not operational: Clock Skew > Data Delay ; ram:inst1|data_out[7] ; state:inst2|next_state.s4 ; clk ; clk ; None ; None ; 3.787 ns ;
; Not operational: Clock Skew > Data Delay ; ram:inst1|data_out[7] ; state:inst2|next_state.s0 ; clk ; clk ; None ; None ; 4.129 ns ;
+------------------------------------------+-----------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; tsu ;
+-----------------------------------------+--------------------------------------⌨️ 快捷键说明
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