dd.vhd

来自「这是一个用VHDL +图形法在CPLD内部搭建的液晶显示的驱动程序。液晶是ocm」· VHDL 代码 · 共 25 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY dd IS
  PORT (s0             :IN std_logic;
        wr            :IN std_logic; 
        s1       :OUT std_logic
       
       );
END dd;
ARCHITECTURE behave OF dd IS
--signal reg:std_logic;
BEGIN  
process(s0,wr)
begin
 if wr='1' then
     s1<='0';
 elsif rising_edge(s0) then
     s1<=s0;
 end if;
end process;
end behave;