lcd.flow.rpt

这是一个用VHDL +图形法在CPLD内部搭建的液晶显示的驱动程序。液晶是ocmj5*10系列

Flow report for lcd
Tue Jul 10 15:36:24 2007
Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Flow Summary                                                           ;
+-------------------------+----------------------------------------------+
; Flow Status             ; Successful - Tue Jul 10 15:36:23 2007        ;
; Quartus II Version      ; 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition ;
; Revision Name           ; lcd                                          ;
; Top-level Entity Name   ; lcd                                          ;
; Family                  ; MAX II                                       ;
; Device                  ; EPM1270T144C5                                ;
; Timing Models           ; Final                                        ;
; Met timing requirements ; No                                           ;
; Total logic elements    ; 486 / 1,270 ( 38 % )                         ;
; Total pins              ; 115 / 116 ( 99 % )                           ;
; Total virtual pins      ; 0                                            ;
; UFM blocks              ; 0 / 1 ( 0 % )                                ;
+-------------------------+----------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 07/10/2007 15:35:11 ;
; Main task         ; Compilation         ;
; Revision Name     ; lcd                 ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:15     ;
; Fitter               ; 00:00:21     ;
; Assembler            ; 00:00:02     ;
; Timing Analyzer      ; 00:00:09     ;
; Total                ; 00:00:47     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off lcd -c lcd
quartus_fit --read_settings_files=off --write_settings_files=off lcd -c lcd
quartus_asm --read_settings_files=off --write_settings_files=off lcd -c lcd
quartus_tan --read_settings_files=off --write_settings_files=off lcd -c lcd