lcd.fit.eqn

这是一个用VHDL +图形法在CPLD内部搭建的液晶显示的驱动程序。液晶是ocmj5*10系列

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--D1_req is state:inst2|req at LC_X12_Y7_N2
--operation mode is normal

D1_req_lut_out = D1_next_state.s_b & (J1_3 & !lcd_busy # !J1_3 & (D1_req)) # !D1_next_state.s_b & (D1_req);
D1_req = DFFEAS(D1_req_lut_out, GLOBAL(B1_Q), VCC, , , , , , );


--J1_3 is try:inst9|DFF2:inst|3 at LC_X8_Y10_N3
--operation mode is normal

J1_3_lut_out = VCC;
J1_3 = DFFEAS(J1_3_lut_out, G1_inst12, !H1_s1, , , , , , );


--D1_data_out[7] is state:inst2|data_out[7] at LC_X12_Y8_N4
--operation mode is normal

D1_data_out[7]_lut_out = D1L150 & (D1_data_out[7] & D1L157) # !D1L150 & (D1L159 # D1_data_out[7] & D1L157);
D1_data_out[7] = DFFEAS(D1_data_out[7]_lut_out, GLOBAL(B1_Q), VCC, , J1_3, , , , );


--D1_data_out[6] is state:inst2|data_out[6] at LC_X11_Y9_N0
--operation mode is normal

D1_data_out[6]_lut_out = D1_next_state.s2 & (E1_19) # !D1_next_state.s2 & (D1L160 # D1L161);
D1_data_out[6] = DFFEAS(D1_data_out[6]_lut_out, GLOBAL(B1_Q), VCC, , D1L32, , , , );


--D1_data_out[5] is state:inst2|data_out[5] at LC_X11_Y9_N2
--operation mode is normal

D1_data_out[5]_lut_out = D1_next_state.s2 & E1_18 # !D1_next_state.s2 & (D1L162);
D1_data_out[5] = DFFEAS(D1_data_out[5]_lut_out, GLOBAL(B1_Q), VCC, , D1L32, , , , );


--D1_data_out[4] is state:inst2|data_out[4] at LC_X12_Y9_N5
--operation mode is normal

D1_data_out[4]_lut_out = D1L164 # D1L182 # D1L34 & D1L167;
D1_data_out[4] = DFFEAS(D1_data_out[4]_lut_out, GLOBAL(B1_Q), VCC, , J1_3, , , , );


--D1_data_out[3] is state:inst2|data_out[3] at LC_X12_Y8_N6
--operation mode is normal

D1_data_out[3]_lut_out = D1L169 # D1L183 # D1_data_out[3] & D1L171;
D1_data_out[3] = DFFEAS(D1_data_out[3]_lut_out, GLOBAL(B1_Q), VCC, , J1_3, , , , );


--D1_data_out[2] is state:inst2|data_out[2] at LC_X11_Y9_N3
--operation mode is normal

D1_data_out[2]_lut_out = D1L173 & (!D1L155 # !D1L50 # !D1L24);
D1_data_out[2] = DFFEAS(D1_data_out[2]_lut_out, GLOBAL(B1_Q), VCC, , D1L32, , , , );


--D1_data_out[1] is state:inst2|data_out[1] at LC_X11_Y9_N8
--operation mode is normal

D1_data_out[1]_lut_out = D1L175 & (!D1L155 # !D1L50 # !D1L24);
D1_data_out[1] = DFFEAS(D1_data_out[1]_lut_out, GLOBAL(B1_Q), VCC, , D1L32, , , , );


--D1_data_out[0] is state:inst2|data_out[0] at LC_X12_Y8_N9
--operation mode is normal

D1_data_out[0]_lut_out = D1_data_out[0] & (D1L171 # D1L178) # !D1_data_out[0] & !D1L150 & (D1L178);
D1_data_out[0] = DFFEAS(D1_data_out[0]_lut_out, GLOBAL(B1_Q), VCC, , J1_3, , , , );


--D1_next_state.s_b is state:inst2|next_state.s_b at LC_X12_Y7_N4
--operation mode is normal

D1_next_state.s_b_lut_out = !D1_next_state.s8 & D1L24 # !D1_req # !lcd_busy;
D1_next_state.s_b = DFFEAS(D1_next_state.s_b_lut_out, GLOBAL(B1_Q), VCC, , J1_3, , , , );


--B1_Q is freq:inst|Q at LC_X12_Y3_N8
--operation mode is normal

B1_Q_lut_out = B1_Q $ (B1L27 & B1_i[0] & B1L28);
B1_Q = DFFEAS(B1_Q_lut_out, GLOBAL(clk), VCC, , , , , , );


--A1L95 is inst14~37 at LC_X9_Y10_N8
--operation mode is normal

A1L95 = !E1_14 & !E1_15 & !xwe;


--G1_inst12 is try:inst9|inst12 at LC_X9_Y10_N9
--operation mode is normal

G1_inst12 = E1_12 & E1_13 & E1_16 & A1L95;


--H1_s1 is dd:inst10|s1 at LC_X9_Y10_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

H1_s1_lut_out = GND;
H1_s1 = DFFEAS(H1_s1_lut_out, D1_clear, !inst14, , , D1_clear, , , VCC);


--D1L150 is state:inst2|process0~225 at LC_X12_Y7_N7
--operation mode is normal

D1L150 = lcd_busy # D1_req;


--D1_next_state.s9 is state:inst2|next_state.s9 at LC_X11_Y8_N2
--operation mode is normal

D1_next_state.s9_lut_out = D1L152 & (D1L153 # D1_next_state.s9 & !D1L179) # !D1L152 & D1_next_state.s9 & (!D1L179);
D1_next_state.s9 = DFFEAS(D1_next_state.s9_lut_out, GLOBAL(B1_Q), VCC, , J1_3, , , , );


--D1L24 is state:inst2|data_out[2]~794 at LC_X11_Y8_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_next_state.s3_qfbk = D1_next_state.s3;
D1L24 = !D1_next_state.s3_qfbk & !D1_next_state.s9;

--D1_next_state.s3 is state:inst2|next_state.s3 at LC_X11_Y8_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_next_state.s3 = DFFEAS(D1L24, GLOBAL(B1_Q), VCC, , D1L149, D1_next_state.s2, , , VCC);


--D1L155 is state:inst2|Select~3585 at LC_X12_Y9_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_next_state.s1_qfbk = D1_next_state.s1;
D1L155 = !D1_next_state.s5 & !D1_next_state.s6 & !D1_next_state.s1_qfbk;

--D1_next_state.s1 is state:inst2|next_state.s1 at LC_X12_Y9_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_next_state.s1 = DFFEAS(D1L155, GLOBAL(B1_Q), VCC, , D1L149, D1_next_state.s0, , , VCC);


--D1L25 is state:inst2|data_out[2]~795 at LC_X12_Y7_N5
--operation mode is normal

D1L25 = !D1_next_state.s7 & D1L155 & D1L24 & !D1_next_state.s8;


--D1_next_state.s4 is state:inst2|next_state.s4 at LC_X11_Y8_N5
--operation mode is normal

D1_next_state.s4_lut_out = D1L152 & (D1_next_state.s4 & !D1L179) # !D1L152 & (D1L153 # D1_next_state.s4 & !D1L179);
D1_next_state.s4 = DFFEAS(D1_next_state.s4_lut_out, GLOBAL(B1_Q), VCC, , J1_3, , , , );


--D1_next_state.s0 is state:inst2|next_state.s0 at LC_X12_Y7_N9
--operation mode is normal

D1_next_state.s0_lut_out = D1_next_state.s_b & D1_next_state.s0 & !D1L179 # !D1_next_state.s_b & (D1_next_state.s0 & !D1L179 # !D1L180);
D1_next_state.s0 = DFFEAS(D1_next_state.s0_lut_out, GLOBAL(B1_Q), VCC, , J1_3, , , , );


--D1L156 is state:inst2|Select~3586 at LC_X12_Y7_N6
--operation mode is normal

D1L156 = !D1_next_state.s0 & D1_next_state.s_b & !D1_next_state.s4;


--D1L157 is state:inst2|Select~3587 at LC_X12_Y8_N3
--operation mode is normal

D1L157 = D1L150 & (D1_next_state.s2 # !D1L25) # !D1L156;


--C1_data_out[7] is ram:inst1|data_out[7] at LC_X10_Y8_N4
--operation mode is normal

C1_data_out[7]_lut_out = D1_i[4] & (C1L275) # !D1_i[4] & C1L285;
C1_data_out[7] = DFFEAS(C1_data_out[7]_lut_out, GLOBAL(clk), VCC, , , , , , );


--D1L158 is state:inst2|Select~3588 at LC_X11_Y8_N9
--operation mode is normal

D1L158 = D1_next_state.s0 # D1_next_state.s4 # C1_data_out[7] & !D1L24;


--C1_data_out[6] is ram:inst1|data_out[6] at LC_X8_Y6_N9
--operation mode is normal

C1_data_out[6]_lut_out = D1_i[4] & C1L295 # !D1_i[4] & (C1L305);
C1_data_out[6] = DFFEAS(C1_data_out[6]_lut_out, GLOBAL(clk), VCC, , , , , , );


--C1_data_out[5] is ram:inst1|data_out[5] at LC_X4_Y10_N5
--operation mode is normal

C1_data_out[5]_lut_out = D1_i[4] & C1L315 # !D1_i[4] & (C1L325);
C1_data_out[5] = DFFEAS(C1_data_out[5]_lut_out, GLOBAL(clk), VCC, , , , , , );


--D1L127 is state:inst2|LessThan~741 at LC_X11_Y8_N7
--operation mode is normal

D1L127 = C1_data_out[5] # C1_data_out[6];


--D1L50 is state:inst2|i[4]~706 at LC_X12_Y9_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_next_state.s7_qfbk = D1_next_state.s7;
D1L50 = !D1_next_state.s7_qfbk & !D1_next_state.s8;

--D1_next_state.s7 is state:inst2|next_state.s7 at LC_X12_Y9_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_next_state.s7 = DFFEAS(D1L50, GLOBAL(B1_Q), VCC, , D1L149, D1_next_state.s6, , , VCC);


--D1L159 is state:inst2|Select~3589 at LC_X11_Y8_N6
--operation mode is normal

D1L159 = D1L158 # !D1L50 & (C1_data_out[7] $ D1L127);


--D1L160 is state:inst2|Select~3591 at LC_X11_Y9_N7
--operation mode is normal

D1L160 = D1L50 & D1L155 & (D1L24 # C1_data_out[6]);


--D1L161 is state:inst2|Select~3592 at LC_X11_Y8_N8
--operation mode is normal

D1L161 = D1_next_state.s7 & (C1_data_out[5] $ !C1_data_out[6]) # !D1_next_state.s7 & D1_next_state.s8 & (C1_data_out[5] $ !C1_data_out[6]);


--D1L32 is state:inst2|data_out[6]~796 at LC_X12_Y7_N8
--operation mode is normal

D1L32 = D1_next_state.s_b & !D1_req & !lcd_busy & J1_3;


--D1L162 is state:inst2|Select~3594 at LC_X11_Y9_N9
--operation mode is normal

D1L162 = D1L50 & D1L155 & (C1_data_out[5] # D1L24) # !D1L50 & (!C1_data_out[5]);


--D1L163 is state:inst2|Select~3596 at LC_X12_Y9_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_next_state.s2_qfbk = D1_next_state.s2;
D1L163 = !D1_next_state.s5 & !D1_next_state.s6 & !D1_next_state.s2_qfbk & !D1_next_state.s1;

--D1_next_state.s2 is state:inst2|next_state.s2 at LC_X12_Y9_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_next_state.s2 = DFFEAS(D1L163, GLOBAL(B1_Q), VCC, , D1L149, D1_next_state.s1, , , VCC);


--D1L164 is state:inst2|Select~3597 at LC_X12_Y8_N1
--operation mode is normal

D1L164 = D1_data_out[4] & (!D1L163 & D1L150 # !D1L156);


--D1L165 is state:inst2|Select~3598 at LC_X12_Y9_N8
--operation mode is normal

D1L165 = D1_next_state.s0 # D1_next_state.s4 # D1_next_state.s2 & E1_17;


--D1L1 is state:inst2|add~1180 at LC_X10_Y9_N6
--operation mode is normal

D1L1_carry_eqn = (!D1L6 & D1L3) # (D1L6 & D1L4);
D1L1 = D1L1_carry_eqn $ D1_i[5];


--D1_i[4] is state:inst2|i[4] at LC_X8_Y5_N8
--operation mode is arithmetic

D1_i[4]_carry_eqn = (!D1L37 & D1L45) # (D1L37 & D1L46);
D1_i[4]_lut_out = D1_i[4] $ (!D1_i[4]_carry_eqn);
D1_i[4] = DFFEAS(D1_i[4]_lut_out, GLOBAL(B1_Q), VCC, , D1L53, , , D1L48, );

--D1L51 is state:inst2|i[4]~708 at LC_X8_Y5_N8
--operation mode is arithmetic

D1L51_cout_0 = D1_i[4] & (!D1L45);
D1L51 = CARRY(D1L51_cout_0);

--D1L52 is state:inst2|i[4]~708COUT1_870 at LC_X8_Y5_N8
--operation mode is arithmetic

D1L52_cout_1 = D1_i[4] & (!D1L46);
D1L52 = CARRY(D1L52_cout_1);


--D1L166 is state:inst2|Select~3599 at LC_X12_Y9_N3
--operation mode is normal

D1L166 = D1_i[4] & (D1_next_state.s1 # D1L1 & D1_next_state.s5) # !D1_i[4] & D1L1 & D1_next_state.s5;


--D1L167 is state:inst2|Select~3600 at LC_X12_Y9_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_next_state.s8_qfbk = D1_next_state.s8;
D1L167 = D1_next_state.s9 # D1_next_state.s7 # D1_next_state.s8_qfbk # D1_next_state.s3;

--D1_next_state.s8 is state:inst2|next_state.s8 at LC_X12_Y9_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_next_state.s8 = DFFEAS(D1L167, GLOBAL(B1_Q), VCC, , D1L149, D1_next_state.s7, , , VCC);


--C1_data_out[4] is ram:inst1|data_out[4] at LC_X6_Y8_N9
--operation mode is normal

C1_data_out[4]_lut_out = D1_i[4] & C1L335 # !D1_i[4] & (C1L345);
C1_data_out[4] = DFFEAS(C1_data_out[4]_lut_out, GLOBAL(clk), VCC, , , , , , );


--D1L34 is state:inst2|data_out~797 at LC_X12_Y8_N2
--operation mode is normal

D1L34 = lcd_busy & D1_data_out[4] # !lcd_busy & (D1_req & D1_data_out[4] # !D1_req & (C1_data_out[4]));


--D1_i[3] is state:inst2|i[3] at LC_X8_Y5_N7
--operation mode is arithmetic

D1_i[3]_carry_eqn = (!D1L37 & D1L42) # (D1L37 & D1L43);
D1_i[3]_lut_out = D1_i[3] $ D1_i[3]_carry_eqn;
D1_i[3] = DFFEAS(D1_i[3]_lut_out, GLOBAL(B1_Q), VCC, , D1L53, , , D1L48, );

--D1L45 is state:inst2|i[3]~712 at LC_X8_Y5_N7
--operation mode is arithmetic

D1L45_cout_0 = !D1L42 # !D1_i[3];
D1L45 = CARRY(D1L45_cout_0);

--D1L46 is state:inst2|i[3]~712COUT1_868 at LC_X8_Y5_N7
--operation mode is arithmetic

D1L46_cout_1 = !D1L43 # !D1_i[3];
D1L46 = CARRY(D1L46_cout_1);


--D1L2 is state:inst2|add~1185 at LC_X10_Y9_N5