pcireadme2.txt

LEON3 SOC environment, PCI bridges.

To simulate the PCI core with leon3, you should use the pci_top2 test bench. 
This test bench includes leon3 system with a PCI master/target with DMA, a 
leon3 system with PCI target (PCI address 0x44000000) and PCI Host.

The PCI host configure the PCI system at the start of the simulation.

The PCI target AHB mapping is done in the "boott.S" assembler file.
This system has SRAM memory at address 0x40000000 (with some waitstate)
and AHBRAM at address 0xD0000000 (with no waitstate).

The PCI master (and DMA) is controlled by the "prog.c" C-program.
This system has the same memory structure as the PCI target system.
The C-program writes to the target (using DMA write) and then reads the data 
back (using DMA read). The data is compared and if the data is equal, "0E" is
written to the memory at address (DMA burst length) + 2. If the data is not
equal, "1E" is written to memory at the same address.

The simulation is ended with a "** Failure: *** IU in error mode, test failed!"
message.