tkconfig.h

Clock gating logic for LEON3 processor.

#ifndef CONFIG_DSU_JTAG
#define CONFIG_DSU_JTAG 0
#endif

#ifndef CONFIG_DSU_ETH
#define CONFIG_DSU_ETH 0
#endif

#ifndef CONFIG_DSU_IPMSB
#define CONFIG_DSU_IPMSB C0A8
#endif

#ifndef CONFIG_DSU_IPLSB
#define CONFIG_DSU_IPLSB 0033
#endif

#ifndef CONFIG_DSU_ETHMSB
#define CONFIG_DSU_ETHMSB 00007A
#endif

#ifndef CONFIG_DSU_ETHLSB
#define CONFIG_DSU_ETHLSB CC0001
#endif

#if defined CONFIG_DSU_ETHSZ1
#define CFG_DSU_ETHB 1
#elif CONFIG_DSU_ETHSZ2
#define CFG_DSU_ETHB 2
#elif CONFIG_DSU_ETHSZ4
#define CFG_DSU_ETHB 4
#elif CONFIG_DSU_ETHSZ8
#define CFG_DSU_ETHB 8
#elif CONFIG_DSU_ETHSZ16
#define CFG_DSU_ETHB 16
#elif CONFIG_DSU_ETHSZ32
#define CFG_DSU_ETHB 32
#else
#define CFG_DSU_ETHB 1
#endif


#ifndef CONFIG_SRCTRL
#define CONFIG_SRCTRL 0
#endif

#ifndef CONFIG_SRCTRL_PROMWS
#define CONFIG_SRCTRL_PROMWS 0
#endif

#ifndef CONFIG_SRCTRL_RAMWS
#define CONFIG_SRCTRL_RAMWS 0
#endif

#ifndef CONFIG_SRCTRL_IOWS
#define CONFIG_SRCTRL_IOWS 0
#endif

#ifndef CONFIG_SRCTRL_RMW
#define CONFIG_SRCTRL_RMW 0
#endif

#ifndef CONFIG_SRCTRL_8BIT
#define CONFIG_SRCTRL_8BIT 0
#endif


#ifndef CONFIG_SRCTRL_ROMASEL
#define CONFIG_SRCTRL_ROMASEL 0
#endif

#if defined CONFIG_SRCTRL_SRBANKS1
#define CFG_SR_CTRL_SRBANKS 1
#elif defined CONFIG_SRCTRL_SRBANKS2
#define CFG_SR_CTRL_SRBANKS 2
#elif defined CONFIG_SRCTRL_SRBANKS3
#define CFG_SR_CTRL_SRBANKS 3
#elif defined CONFIG_SRCTRL_SRBANKS4
#define CFG_SR_CTRL_SRBANKS 4
#elif defined CONFIG_SRCTRL_SRBANKS5
#define CFG_SR_CTRL_SRBANKS 5
#else
#define CFG_SR_CTRL_SRBANKS 1
#endif

#if defined CONFIG_SRCTRL_BANKSZ0
#define CFG_SR_CTRL_BANKSZ 0
#elif defined CONFIG_SRCTRL_BANKSZ1
#define CFG_SR_CTRL_BANKSZ 1
#elif defined CONFIG_SRCTRL_BANKSZ2
#define CFG_SR_CTRL_BANKSZ 2
#elif defined CONFIG_SRCTRL_BANKSZ3
#define CFG_SR_CTRL_BANKSZ 3
#elif defined CONFIG_SRCTRL_BANKSZ4
#define CFG_SR_CTRL_BANKSZ 4
#elif defined CONFIG_SRCTRL_BANKSZ5
#define CFG_SR_CTRL_BANKSZ 5
#elif defined CONFIG_SRCTRL_BANKSZ6
#define CFG_SR_CTRL_BANKSZ 6
#elif defined CONFIG_SRCTRL_BANKSZ7
#define CFG_SR_CTRL_BANKSZ 7
#elif defined CONFIG_SRCTRL_BANKSZ8
#define CFG_SR_CTRL_BANKSZ 8
#elif defined CONFIG_SRCTRL_BANKSZ9
#define CFG_SR_CTRL_BANKSZ 9
#elif defined CONFIG_SRCTRL_BANKSZ10
#define CFG_SR_CTRL_BANKSZ 10
#elif defined CONFIG_SRCTRL_BANKSZ11
#define CFG_SR_CTRL_BANKSZ 11
#elif defined CONFIG_SRCTRL_BANKSZ12
#define CFG_SR_CTRL_BANKSZ 12
#elif defined CONFIG_SRCTRL_BANKSZ13
#define CFG_SR_CTRL_BANKSZ 13
#else
#define CFG_SR_CTRL_BANKSZ 0
#endif
#ifndef CONFIG_MCTRL_LEON2
#define CONFIG_MCTRL_LEON2 0
#endif

#ifndef CONFIG_MCTRL_SDRAM
#define CONFIG_MCTRL_SDRAM 0
#endif

#ifndef CONFIG_MCTRL_SDRAM_SEPBUS
#define CONFIG_MCTRL_SDRAM_SEPBUS 0
#endif

#ifndef CONFIG_MCTRL_SDRAM_INVCLK
#define CONFIG_MCTRL_SDRAM_INVCLK 0
#endif

#ifndef CONFIG_MCTRL_SDRAM_BUS64
#define CONFIG_MCTRL_SDRAM_BUS64 0
#endif

#ifndef CONFIG_MCTRL_8BIT
#define CONFIG_MCTRL_8BIT 0
#endif

#ifndef CONFIG_MCTRL_16BIT
#define CONFIG_MCTRL_16BIT 0
#endif

#ifndef CONFIG_MCTRL_5CS
#define CONFIG_MCTRL_5CS 0
#endif

#ifndef CONFIG_MCTRL_EDAC
#define CONFIG_MCTRL_EDAC 0
#endif


#ifndef CONFIG_SDCTRL
#define CONFIG_SDCTRL 0
#endif

#ifndef CONFIG_SDCTRL_SEPBUS
#define CONFIG_SDCTRL_SEPBUS 0
#endif

#ifndef CONFIG_SDCTRL_INVCLK
#define CONFIG_SDCTRL_INVCLK 0
#endif

#ifndef CONFIG_SDCTRL_BUS64
#define CONFIG_SDCTRL_BUS64 0
#endif

#ifndef CONFIG_AHBROM_ENABLE
#define CONFIG_AHBROM_ENABLE 0
#endif

#ifndef CONFIG_AHBROM_START
#define CONFIG_AHBROM_START 000
#endif

#ifndef CONFIG_AHBROM_PIPE
#define CONFIG_AHBROM_PIPE 0
#endif

#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
#define CONFIG_ROM_START 100
#else
#define CONFIG_ROM_START 000
#endif


#ifndef CONFIG_AHBRAM_ENABLE
#define CONFIG_AHBRAM_ENABLE 0
#endif

#ifndef CONFIG_AHBRAM_START
#define CONFIG_AHBRAM_START A00
#endif

#if defined CONFIG_AHBRAM_SZ1
#define CFG_AHBRAMSZ 1
#elif CONFIG_AHBRAM_SZ2
#define CFG_AHBRAMSZ 2
#elif CONFIG_AHBRAM_SZ4
#define CFG_AHBRAMSZ 4
#elif CONFIG_AHBRAM_SZ8
#define CFG_AHBRAMSZ 8
#elif CONFIG_AHBRAM_SZ16
#define CFG_AHBRAMSZ 16
#elif CONFIG_AHBRAM_SZ32
#define CFG_AHBRAMSZ 32
#elif CONFIG_AHBRAM_SZ64
#define CFG_AHBRAMSZ 64
#else
#define CFG_AHBRAMSZ 1
#endif

#ifndef CONFIG_GRETH_ENABLE
#define CONFIG_GRETH_ENABLE 0
#endif

#ifndef CONFIG_GRETH_GIGA
#define CONFIG_GRETH_GIGA 0
#endif

#if defined CONFIG_GRETH_FIFO4
#define CFG_GRETH_FIFO 4
#elif defined CONFIG_GRETH_FIFO8
#define CFG_GRETH_FIFO 8
#elif defined CONFIG_GRETH_FIFO16
#define CFG_GRETH_FIFO 16
#elif defined CONFIG_GRETH_FIFO32
#define CFG_GRETH_FIFO 32
#elif defined CONFIG_GRETH_FIFO64
#define CFG_GRETH_FIFO 64
#else
#define CFG_GRETH_FIFO 8
#endif

#ifndef CONFIG_CAN_ENABLE
#define CONFIG_CAN_ENABLE 0
#endif

#ifndef CONFIG_CANIO
#define CONFIG_CANIO 0
#endif

#ifndef CONFIG_CANIRQ
#define CONFIG_CANIRQ 0
#endif

#ifndef CONFIG_CANLOOP
#define CONFIG_CANLOOP 0
#endif

#ifndef CONFIG_CAN_SYNCRST
#define CONFIG_CAN_SYNCRST 0
#endif


#ifndef CONFIG_CAN_FT
#define CONFIG_CAN_FT 0
#endif
#if defined CONFIG_PCI_SIMPLE_TARGET
#define CFG_PCITYPE 1
#elif defined CONFIG_PCI_MASTER_TARGET_DMA
#define CFG_PCITYPE 3
#elif defined CONFIG_PCI_MASTER_TARGET
#define CFG_PCITYPE 2
#else
#define CFG_PCITYPE 0
#endif

#ifndef CONFIG_PCI_VENDORID
#define CONFIG_PCI_VENDORID 0
#endif

#ifndef CONFIG_PCI_DEVICEID
#define CONFIG_PCI_DEVICEID 0
#endif

#ifndef CONFIG_PCI_REVID
#define CONFIG_PCI_REVID 0
#endif

#if defined CONFIG_PCI_FIFO0
#define CFG_PCIFIFO 8
#define CFG_PCI_ENFIFO 0
#elif defined CONFIG_PCI_FIFO16
#define CFG_PCIFIFO 16
#elif defined CONFIG_PCI_FIFO32
#define CFG_PCIFIFO 32
#elif defined CONFIG_PCI_FIFO64
#define CFG_PCIFIFO 64
#elif defined CONFIG_PCI_FIFO128
#define CFG_PCIFIFO 128
#elif defined CONFIG_PCI_FIFO256
#define CFG_PCIFIFO 256
#else
#define CFG_PCIFIFO 8
#endif

#ifndef CFG_PCI_ENFIFO
#define CFG_PCI_ENFIFO 1
#endif


#ifndef CONFIG_PCI_ARBITER_APB
#define CONFIG_PCI_ARBITER_APB 0
#endif

#ifndef CONFIG_PCI_ARBITER
#define CONFIG_PCI_ARBITER 0
#endif

#ifndef CONFIG_PCI_TRACE
#define CONFIG_PCI_TRACE 0
#endif

#if defined CONFIG_PCI_TRACE512
#define CFG_PCI_TRACEBUF 512
#elif defined CONFIG_PCI_TRACE1024
#define CFG_PCI_TRACEBUF 1024
#elif defined CONFIG_PCI_TRACE2048
#define CFG_PCI_TRACEBUF 2048
#elif defined CONFIG_PCI_TRACE4096
#define CFG_PCI_TRACEBUF 4096
#else
#define CFG_PCI_TRACEBUF 256
#endif


#ifndef CONFIG_SPW_ENABLE
#define CONFIG_SPW_ENABLE 0
#endif

#ifndef CONFIG_SPW_NUM
#define CONFIG_SPW_NUM 1
#endif

#if defined CONFIG_SPW_AHBFIFO4
#define CONFIG_SPW_AHBFIFO 4
#elif defined CONFIG_SPW_AHBFIFO8
#define CONFIG_SPW_AHBFIFO 8
#elif defined CONFIG_SPW_AHBFIFO16
#define CONFIG_SPW_AHBFIFO 16
#elif defined CONFIG_SPW_AHBFIFO32
#define CONFIG_SPW_AHBFIFO 32
#elif defined CONFIG_SPW_AHBFIFO64
#define CONFIG_SPW_AHBFIFO 64
#else
#define CONFIG_SPW_AHBFIFO 4
#endif

#if defined CONFIG_SPW_RXFIFO16
#define CONFIG_SPW_RXFIFO 16
#elif defined CONFIG_SPW_RXFIFO32
#define CONFIG_SPW_RXFIFO 32
#elif defined CONFIG_SPW_RXFIFO64
#define CONFIG_SPW_RXFIFO 64
#else
#define CONFIG_SPW_RXFIFO 16
#endif

#ifndef CONFIG_SPW_RMAP
#define CONFIG_SPW_RMAP 0
#endif

#if defined CONFIG_SPW_RMAPBUF2
#define CONFIG_SPW_RMAPBUF 2
#elif defined CONFIG_SPW_RMAPBUF4
#define CONFIG_SPW_RMAPBUF 4
#elif defined CONFIG_SPW_RMAPBUF6
#define CONFIG_SPW_RMAPBUF 6
#elif defined CONFIG_SPW_RMAPBUF8
#define CONFIG_SPW_RMAPBUF 8
#else
#define CONFIG_SPW_RMAPBUF 4
#endif

#ifndef CONFIG_SPW_RMAPCRC
#define CONFIG_SPW_RMAPCRC 0
#endif

#ifndef CONFIG_UART1_ENABLE
#define CONFIG_UART1_ENABLE 0
#endif

#if defined CONFIG_UA1_FIFO1
#define CFG_UA1_FIFO 1
#elif defined CONFIG_UA1_FIFO2
#define CFG_UA1_FIFO 2
#elif defined CONFIG_UA1_FIFO4
#define CFG_UA1_FIFO 4
#elif defined CONFIG_UA1_FIFO8
#define CFG_UA1_FIFO 8
#elif defined CONFIG_UA1_FIFO16
#define CFG_UA1_FIFO 16
#elif defined CONFIG_UA1_FIFO32
#define CFG_UA1_FIFO 32
#else
#define CFG_UA1_FIFO 1
#endif

#ifndef CONFIG_UART2_ENABLE
#define CONFIG_UART2_ENABLE 0
#endif

#if defined CONFIG_UA2_FIFO1
#define CFG_UA2_FIFO 1
#elif defined CONFIG_UA2_FIFO2
#define CFG_UA2_FIFO 2
#elif defined CONFIG_UA2_FIFO4
#define CFG_UA2_FIFO 4
#elif defined CONFIG_UA2_FIFO8
#define CFG_UA2_FIFO 8
#elif defined CONFIG_UA2_FIFO16
#define CFG_UA2_FIFO 16
#elif defined CONFIG_UA2_FIFO32
#define CFG_UA2_FIFO 32
#else
#define CFG_UA2_FIFO 1
#endif

#ifndef CONFIG_IRQ3_ENABLE
#define CONFIG_IRQ3_ENABLE 0
#endif
#ifndef CONFIG_GPT_ENABLE
#define CONFIG_GPT_ENABLE 0
#endif

#ifndef CONFIG_GPT_NTIM
#define CONFIG_GPT_NTIM 1
#endif

#ifndef CONFIG_GPT_SW
#define CONFIG_GPT_SW 8
#endif

#ifndef CONFIG_GPT_TW
#define CONFIG_GPT_TW 8
#endif

#ifndef CONFIG_GPT_IRQ
#define CONFIG_GPT_IRQ 8
#endif

#ifndef CONFIG_GPT_SEPIRQ
#define CONFIG_GPT_SEPIRQ 0
#endif
#ifndef CONFIG_GPT_ENABLE
#define CONFIG_GPT_ENABLE 0
#endif

#ifndef CONFIG_GPT_NTIM
#define CONFIG_GPT_NTIM 1
#endif

#ifndef CONFIG_GPT_SW
#define CONFIG_GPT_SW 8
#endif

#ifndef CONFIG_GPT_TW
#define CONFIG_GPT_TW 8
#endif

#ifndef CONFIG_GPT_IRQ
#define CONFIG_GPT_IRQ 8
#endif

#ifndef CONFIG_GPT_SEPIRQ
#define CONFIG_GPT_SEPIRQ 0
#endif

#ifndef CONFIG_GPT_WDOGEN
#define CONFIG_GPT_WDOGEN 0
#endif

#ifndef CONFIG_GPT_WDOG
#define CONFIG_GPT_WDOG 0
#endif

#ifndef CONFIG_GRGPIO_ENABLE
#define CONFIG_GRGPIO_ENABLE 0
#endif
#ifndef CONFIG_GRGPIO_IMASK
#define CONFIG_GRGPIO_IMASK 0000
#endif
#ifndef CONFIG_GRGPIO_WIDTH
#define CONFIG_GRGPIO_WIDTH 1
#endif


#ifndef CONFIG_DEBUG_UART
#define CONFIG_DEBUG_UART 0
#endif