config.help

Clock gating logic for LEON3 processor.

  and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000
  board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards.

64-bit data bus
CONFIG_MCTRL_SDRAM_BUS64
  Say Y here to enable 64-bit SDRAM data bus.

SDRAM controller enable
CONFIG_SDCTRL
  Say Y here to enabled a 32/64-bit PC133 SDRAM controller. 

SDRAM controller inverted clock
CONFIG_SDCTRL_INVCLK
  If you say Y here, the SDRAM clock will be inverted in respect to the
  system clock and the SDRAM signals. This will limit the SDRAM frequency
  to 50/66 MHz, but has the benefit that you will not need a PLL to
  generate the SDRAM clock. On FPGA targets, say Y. On ASIC targets,
  say N and tell your foundry to balance the SDRAM clock output.

64-bit data bus
CONFIG_SDCTRL_BUS64
  Say Y here to enable 64-bit data bus.

On-chip rom
CONFIG_AHBROM_ENABLE
  Say Y here to add a block on on-chip rom to the AHB bus. The ram
  provides 0-waitstates read access,  burst support, and 8-, 16- 
  and 32-bit data size. The rom will be syntheised into block rams
  on Xilinx and Altera FPGA devices, and into gates on ASIC 
  technologies. GRLIB includes a utility to automatically create
  the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB
  documentation for details.

On-chip rom address
CONFIG_AHBROM_START
  Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy
  a 1 Mbyte slot at the selected address. Default is 000, corresponding
  to AHB address 0x00000000. When address 0x0 is selected, the rom area
  of any other memory controller is set to 0x10000000 to avoid conflicts.

Enable pipeline register for on-chip rom
CONFIG_AHBROM_PIPE
  Say Y here to add a data pipeline register to the on-chip rom.
  This should be done when the rom is implemenented in (ASIC) gates,
  or in logic cells on FPGAs. Do not use this option when the rom is
  implemented in block rams. If enabled, the rom will operate with 
  one waitstate.

On-chip ram
CONFIG_AHBRAM_ENABLE
  Say Y here to add a block on on-chip ram to the AHB bus. The ram
  provides 0-waitstates read access and 0/1 waitstates write access.
  All AHB burst types are supported, as well as 8-, 16- and 32-bit
  data size.

On-chip ram size
CONFIG_AHBRAM_SZ1
  Set the size of the on-chip AHB ram. The ram is infered/instantiated
  as four byte-wide ram slices to allow byte and half-word write
  accesses. It is therefore essential that the target package can
  infer byte-wide rams. This is currently supported on the generic,
  virtex, virtex2, proasic and axellerator targets.

On-chip ram address
CONFIG_AHBRAM_START
  Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy
  a 1 Mbyte slot at the selected address. Default is A00, corresponding
  to AHB address 0xA0000000.

Gaisler Ethernet MAC enable
CONFIG_GRETH_ENABLE
  Say Y here to enable the Gaisler Research Ethernet MAC . The MAC has 
  one AHB master interface to read and write packets to memory, and one
  APB slave interface for accessing the control registers. 

Gaisler Ethernet 1G MAC enable
CONFIG_GRETH_GIGA
  Say Y here to enable the Gaisler Research 1000 Mbit Ethernet MAC . 
  The 1G MAC is only available in the commercial version of GRLIB,
  so do NOT enable it if you are using the GPL version.

CONFIG_GRETH_FIFO4
  Set the depth of the receive and transmit FIFOs in the MAC core.
  The MAC core will perform AHB burst read/writes with half the
  size of the FIFO depth.


CAN interface enable
CONFIG_CAN_ENABLE
  Say Y here to enable the CAN interace from OpenCores. The core has one
  AHB slave interface for accessing the control registers. The CAN core
  ir register-compatible with the SAJ1000 core from Philips.

CAN register address
CONFIG_CANIO
  The control registers of the CAN core occupy 4 kbyte, and are 
  mapped in the AHB bus I/O area (0xFFF00000 - 0xFFFFF000). This setting
  defines at which address in the I/O area the registers appear (HADDR[19:8]).

CAN interrupt
CONFIG_CANIRQ
  Defines which interrupt number the CAN core will generate.

CAN loob-back testing
CONFIG_CANLOOP
  If you say Y here, the receiver and trasmitter of the CAN core will
  be connected together in a loop-back fashion. This will make it 
  possible to perform loop-back test, but not data will be sent
  or received from the outside. ONLY for testing!

CAN Synchronous reset
CONFIG_CAN_SYNCRST
  If you say Y here, the CAN core will be implemented with
  synchronous reset rather than asynchronous. This is needed
  when the target library does not implement registers with
  async reset. Unless you know what you are doing, say N.

CAN FT memories
CONFIG_CAN_FT
  If you say Y here, the CAN FIFOs will be implemented using
  SEU protected RAM blocks. Only applicable to the FT version
  of grlib.
PCI interface type
CONFIG_PCI_SIMPLE_TARGET
  The target-only PCI interface provides a simple target interface
  without fifos. It is small and robust, and is suitable to be used
  for DSU communications via PCI.

PCI interface type
CONFIG_PCI_MASTER_TARGET
  The master-target PCI interface provides a high-performance 32-bit
  PCI interface with configurable FIFOs and optional DMA channel.

PCI interface type
CONFIG_PCI_MASTER_TARGET_DMA
  Say Y here to enable a DMA controller in the PCI master-target core.
  The DMA controller can perform PCI<->memory data transfers
  independently of the processor.

PCI vendor id
CONFIG_PCI_VENDORID
  Sets the PCI vendor ID in the PCI configuration area.

PCI device id
CONFIG_PCI_DEVICEID
  Sets the PCI device ID in the PCI configuration area.

PCI initiator address
CONFIG_PCI_HADDR
  Sets the MSB AHB adress (HADDR[31:20]) of the PCI initiator area.

PCI FIFO depth
CONFIG_PCI_FIFO8
  The number words in the PCI FIFO buffers in the master-target 
  core. The master interface uses four 33-bit wide FIFOs, while the
  target interface uses two. 


PCI arbiter enable
CONFIG_PCI_ARBITER
  To enable a PCI arbiter, say Y here.

PCI APB interface enable
CONFIG_PCI_ARBITER_APB
  Say Y here to enable the APB interface on the PCI arbiter. This makes
  it possible to dynamically re-assign PCI master priorities. See the
  PCI arbiter manual for details.


PCI trace buffer
CONFIG_PCI_TRACE
  The PCI trace buffer implements a simple on-chip logic analyzer
  to trace the PCI signals. The PCI AD bus and most control signals
  are stored in a circular buffer, and can be read out by the DSU
  or any other AHB master. See the manual for detailed operation.
  Only available for target technologies with dual-port rams.

PCI trace buffer depth
CONFIG_PCI_TRACE256
  Select the number of entries in the PCI trace buffer. Each entry
  will use 6 bytes of on-chip (block) ram.


Spacewire link
CONFIG_SPW_ENABLE
  Say Y here to enable one or more Spacewire serial links. The links
  are based on the GRSPW core from Gaisler Research.

Number of spacewire links
CONFIG_SPW_NUM
  Select the number of links to implement. Each link will be a
  separate AHB master and APB slave for configuration.

AHB FIFO depth
CONFIG_SPW_AHBFIFO4
  Select the AHB FIFO depth (in 32-bit words).

RX FIFO depth
CONFIG_SPW_RXFIFO16
  Select the receiver FIFO depth (in bytes).

RMAP protocol
CONFIG_SPW_RMAP
  Enable hardware support for the RMAP protocol (draft C).

RMAP Buffer depth
CONFIG_SPW_RMAPBUF2
  Select the size of the RMAP buffer (in bytes).

RMAP CRC
CONFIG_SPW_RMAPCRC
  Enable hardware calculation of the RMAP CRC checksum
UART1 enable
CONFIG_UART1_ENABLE
  Say Y here to enable UART1, or the console UART. This is needed to
  get any print-out from LEON3 systems regardless of operating system.

UART1 FIFO
CONFIG_UA1_FIFO1
  The UART has configurable transmitt and receive FIFO's, which can
  be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for
  maximum throughput.


UART2 enable
CONFIG_UART2_ENABLE
  Say Y here to enable UART2, or the secondary UART. This UART can be
  used to connect a second console (uClinux) or to control external
  equipment.

UART2 FIFO
CONFIG_UA2_FIFO1
  The UART has configurable transmitt and receive FIFO's, which can
  be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for
  maximum throughput.

LEON3 interrupt controller
CONFIG_IRQ3_ENABLE
  Say Y here to enable the LEON3 interrupt controller. This is needed
  if you want to be able to receive interrupts. Operating systems like
  Linux, RTEMS and eCos needs this option to be enabled. If you intend
  to use the Bare-C run-time and not use interrupts, you could disable
  the interrupt controller and save about 500 gates.

LEON3 interrupt controller broadcast
CONFIG_IRQ3_BROADCAST_ENABLE
  If enabled the broadcast register is used to determine which
  interrupt should be sent to all cpus instead of just the first
  one that consumes it.
Timer module enable
CONFIG_GPT_ENABLE
  Say Y here to enable the Modular Timer Unit. The timer unit consists
  of one common scaler and up to 7 independent timers. The timer unit
  is needed for Linux, RTEMS, eCos and the Bare-C run-times.

Timer module enable
CONFIG_GPT_NTIM
  Set the number of timers in the timer unit (1 - 7).

Scaler width
CONFIG_GPT_SW
  Set the width if the common pre-scaler (2 - 16 bits). The scaler
  is used to divide the system clock down to 1 MHz, so 8 bits should
  be sufficient for most implementations (allows clocks up to 256 MHz).

Timer width
CONFIG_GPT_TW
  Set the width if the timers (2 - 32 bits). 32 bits is recommended
  for the Bare-C run-time, lower values (e.g. 16 bits) can work with
  RTEMS and Linux.

Timer Interrupt
CONFIG_GPT_IRQ
  Set the interrupt number for the first timer. Remaining timers will
  have incrementing interrupts, unless the separate-interrupts option
  below is disabled.

Watchdog enable
CONFIG_GPT_WDOGEN
  Say Y here to enable the watchdog functionality in the timer unit.

Watchdog time-out value
CONFIG_GPT_WDOG
  This value will be loaded in the watchdog timer at reset.

GPIO port
CONFIG_GRGPIO_ENABLE
  Say Y here to enable a general purpose I/O port. The port can be
  configured from 1 - 32 bits, whith each port signal individually
  programmable as input or output. The port signals can also serve
  as interrupt inputs.

GPIO port witdth
CONFIG_GRGPIO_WIDTH
  Number of bits in the I/O port. Must be in the range of 1 - 32.

GPIO interrupt mask
CONFIG_GRGPIO_IMASK
  The I/O port interrupt mask defines which bits in the I/O port
  should be able to create an interrupt. 

UART debugging
CONFIG_DEBUG_UART
  During simulation, the output from the UARTs is printed on the
  simulator console. Since the ratio between the system clock and
  UART baud-rate is quite high, simulating UART output will be very
  slow. If you say Y here, the UARTs will print a character as soon
  as it is stored in the transmitter data register. The transmitter
  ready flag will be permanently set, speeding up simulation. However,
  the output on the UART tx line will be garbled.  Has not impact on
  synthesis, but will cause the LEON test bench to fail.

FPU register tracing
CONFIG_DEBUG_FPURF
  If you say Y here, all writes to the floating-point unit register file
  will be printed on the simulator console.