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Clock gating logic for LEON3 processor.

    </tr>
    <tr>
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">On-chip RAM<br>

      </span></small></td>
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0xA0000000</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0xA0100000 : On-chip
RAM<br>
      </span></small></td>
      <td valign="top"><br>
      </td>
    </tr>
    <tr>
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">UART</span></small></td>
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000900 -
0x80000A00 : Secondary UART<br>
      </span></small></td>
      <td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">3</span></small></td>
    </tr>
  </tbody>
</table>
<br>
<h4><small><span style="font-family: helvetica,arial,sans-serif;">
</span></small></h4>
<h4><span style="font-family: helvetica,arial,sans-serif;">Configuration</span></h4>
<div style="text-align: left;"><small><span style="font-family: helvetica,arial,sans-serif;">The configuartion of
the LEON3MP design is defined through the config package located <a href="config.vhd">config.vhd</a>.
This file can be automatically generated using a GUI based on tkconfig.
To launch the GUI, do 'make xconfig'. After the configuration is
completed, save and
exit the tool and config.vhd will be created automatically.
<br>
<br>
Alternatively, a pre-defined configuration can be installed for two
specific FPGA boards: gr-pci-xc2v and gr-cpci-xc2v. In
this case, set
the BOARD variable in the local <a href="Makefile">Makefile</a> to the
desired board type, and issue the command
'make config' to generate the configuration file.<br>
<br>
<img alt="" src="../share/gui.gif" height="148" width="561"><br>
<br>
<i>Figure 1. LEON3MP configuration GUI</i><br style="font-family: helvetica,arial,sans-serif;">
</span></small><small>
</small></div>
<h4><span style="font-family: helvetica,arial,sans-serif;">Simulation</span></h4>
<small><span style="font-family: helvetica,arial,sans-serif;">To
simulate the testbench, first compile the model for simulation. This
can be done automatically for three different simulators. Execute one
of the following commands:</span><br style="font-family: helvetica,arial,sans-serif;">
</small>
<ul style="font-family: helvetica,arial,sans-serif;">
  <li><small>make vsim</small></li>
  <li><small>make ncsim</small></li>
  <li><small>make ghdl</small></li>
</ul>
<small><span style="font-family: helvetica,arial,sans-serif;">For vsim,
start the simulation with 'vsim testbench' and do 'run 100'. This
should print the current LEON3MP configuration:</span><br style="font-family: helvetica,arial,sans-serif;">
</small><br>
<small><span style="font-family: courier new,courier,monospace;">$ vsim
-c -quiet testbench</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">Reading
/usr/local/model58/tcl/vsim/pref.tcl</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">Reading
/home/jiri/modelsim.tcl</span><br style="font-family: courier new,courier,monospace;">
</small><small><span style="font-family: courier new,courier,monospace;"></span></small><br style="font-family: courier new,courier,monospace;">
<small><span style="font-family: courier new,courier,monospace;"># 5.8</span><br style="font-family: courier new,courier,monospace;">
</small><small><span style="font-family: courier new,courier,monospace;"></span><big><tt>#
VSIM 1&gt; run<br>
# LEON3 Demonstration design<br>
# GRLIB Version 0.13<br>
# Target technology: virtex2 ,&nbsp; memory library: virtex2<br>
# ahbctrl: mst0: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Leon3 SPARC V8
Processor<br>
# ahbctrl: mst1: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AHB Debug UART<br>
# ahbctrl: mst2: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Fast 32-bit PCI
Bridge<br>
# ahbctrl: mst3: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AMBA DMA controller<br>
# ahbctrl: mst5: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OC ethernet AHB
interface<br>
# ahbctrl: slv0: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Simple SRAM
Controller<br>
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; memory at 0x00000000,
size 16 Mbyte, cacheable, prefetch<br>
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; memory at 0x40000000,
size 16 Mbyte, cacheable, prefetch<br>
# ahbctrl: slv1: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AHB/APB Bridge<br>
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; memory at 0x80000000,
size 1 Mbyte<br>
# ahbctrl: slv2: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Leon3 Debug Support
Unit<br>
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; memory at 0x90000000,
size 256 Mbyte<br>
# ahbctrl: slv4: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Fast 32-bit PCI
Bridge<br>
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; memory at 0xe0000000,
size 256 Mbyte<br>
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O port at 0xfff80000,
size 128kbyte<br>
# ahbctrl: slv5: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OC ethernet AHB
interface<br>
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O port at 0xfffb0000,
size 4kbyte<br>
# ahbctrl: slv6: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OC CAN AHB interface<br>
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O port at 0xfffc0000,
size 4kbyte<br>
# ahbctrl: slv7: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Generic AHB SRAM
module<br>
# ahbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; memory at 0xa0000000,
size 1 Mbyte, cacheable, prefetch<br>
# ahbctrl: AHB arbiter/multiplexer rev 1<br>
# ahbctrl: Common I/O area at 0xfff00000, 1 Mbyte<br>
# ahbctrl: Configuration area at 0xfffff000, 4 kbyte<br>
# apbctrl: APB Bridge at 0x80000000 rev 1<br>
# apbctrl: slv1: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Generic UART<br>
# apbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O ports at 0x80000100,
size 256 byte<br>
# apbctrl: slv2: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Multi-processor
Interrupt Ctrl.<br>
# apbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O ports at 0x80000200,
size 256 byte<br>
# apbctrl: slv3: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Modular Timer Unit<br>
# apbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O ports at 0x80000300,
size 256 byte<br>
# apbctrl: slv4: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Fast 32-bit PCI
Bridge<br>
# apbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O ports at 0x80000400,
size 256 byte<br>
# apbctrl: slv5: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AMBA DMA controller<br>
# apbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O ports at 0x80000500,
size 256 byte<br>
# apbctrl: slv7: Gaisler
Research&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; AHB Debug UART<br>
# apbctrl:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I/O ports at 0x80000700,
size 256 byte<br>
# ahbram7: AHB SRAM Module rev 1, 2 kbytes<br>
# can_oc6: Opencores CAN MAC, rev 0, irq 13<br>
# eth_oc5: Wishbone/AHB interface for OC ethernet MAC, irq 12<br>
# eth_oc5: Opencores 10/100 Mbit ethernet MAC, rev 0<br>
# pci_mtf4: 32-bit PCI/AHB bridge&nbsp; rev 0, 2 Mbyte PCI memory BAR,
8-word FIFOs<br>
# dmactrl5: 32-bit DMA controller &amp; AHB/AHB bridge&nbsp; rev 0<br>
# gptimer3: GR Timer Unit rev 0, 16-bit scaler, 1 32-bit timers, irq 8<br>
# irqmp: Multi-processor Interrupt Controller rev 1, #cpu 1<br>
# apbuart1: Generic UART rev 1, irq 2<br>
# srctrl0: 32-bit PROM/SRAM controller rev 0<br>
# ahbuart7: AHB Debug UART rev 0<br>
# dsu3_2: LEON3 Debug support unit<br>
# leon3_0: LEON3 SPARC V8 processor rev 0<br>
# leon3_0: icache 1*4 kbyte, dcache 1*4 kbyte</tt></big><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"></span><span style="font-family: courier new,courier,monospace;"></span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">VSIM 2&gt;
run -all<br>
#<br># **** GRLIB system test starting ****<br>
# Leon3 SPARC V8 Processor<br>
#&nbsp;&nbsp; register file<br>
#&nbsp;&nbsp; multiplier<br>
#&nbsp;&nbsp; radix-2 divider<br>
#&nbsp;&nbsp; cache system<br>
# Multi-processor Interrupt Ctrl.<br>
# Generic UART<br>
# Modular Timer Unit<br>
# Test passed, halting with IU error mode<br>
#<br>
# ** Failure: *** IU in error mode, simulation halted ***<br>
#&nbsp;&nbsp;&nbsp; Time: 669213500 ps&nbsp; Iteration: 1&nbsp; Process: /testbench/iuerr File: testbench.vhd<br>
# Break at testbench.vhd line 263<br>
# Stopped at testbench.vhd line 263<br>
<br>
</span></small><h4><small><span style="font-family: helvetica,arial,sans-serif;">Synthesis<br>
</span></small></h4>
<h4><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></h4>
<small><span style="font-family: helvetica,arial,sans-serif;">To
synthesize and perform place&amp;route for any of the supported
FPGA boards, set the BOARD variable in the Makefile and issue the
appropriate make commands for your tool chain (see GRLIB User's Manual
for details).&nbsp; Alternatively, the design can be implemented using
the graphical XGrlib tool, which is started with 'make xgrlib'.<br>
<br>
<br>
<img alt="" src="../../doc/grlib/xgrlib.gif" height="537" width="619"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">&nbsp;</span></small><br>
<div style="text-align: justify;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></div>
<small><span style="font-family: helvetica,arial,sans-serif;">
<br>
</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><i>Figure 2. XGrlib
implementation tool</i></span></small><br>
<small><span style="font-family: helvetica,arial,sans-serif;"><br>
<br>
For ASIC synthesis, scripts to synthesise LEON3MP towards the Atmel
ATC18 technology are provided. Run either atc18.dc or atc18.rc to
synthesise with Synopsys DC, or Cadence RC.<br>
<br>
</span></small>
<h4><small><span style="font-family: helvetica,arial,sans-serif;">Software
development</span></small></h4>
<h4><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></h4>
<ul>
  <li><small><span style="font-family: helvetica,arial,sans-serif;"><b><a href="http://www.rtems.org/">RTEMS</a>:</b> to
develop RTEMS applications, download and install the <a href="http://www.gaisler.com/products/rcc.html">LEON3 RTEMS
Cross-compiler</a> from gaisler.com. The LEON3 bsp automatically
detects