config.help

LEON3 SOC GRlip IP core. Memory controller.

Instruction cache replacement algorithm
CONFIG_ICACHE_ALGORND
  Cache replacement algorithm for caches with 2 - 4 sets. The 'random'
  algorithm selects the set to evict randomly. The least-recently-used
  (LRR) algorithm evicts the set least recently replaced. The least-
  recently-used (LRU) algorithm evicts the set least recently accessed.
  The random algorithm uses a simple 1- or 2-bit counter to select
  the eviction set and has low area overhead. The LRR scheme uses one
  extra bit in the tag ram and has therefore also low area overhead.
  However, the LRR scheme can only be used with 2-set caches. The LRU
  scheme has typically the best performance but also highest area overhead.
  A 2-set LRU uses 1 flip-flop per line, a 3-set LRU uses 3 flip-flops
  per line, and a 4-set LRU uses 5 flip-flops per line to store the access
  history.

Instruction cache locking
CONFIG_ICACHE_LOCK
  Say Y here to enable cache locking in the instruction cache.
  Locking can be done on cache-line level, but will increase the
  width of the tag ram with one bit. If you don't know what
  locking is good for, it is safe to say N.

Data cache associativity
CONFIG_DCACHE_ASSO1
  The data cache can be implemented as a multi-set cache with
  1 - 4 sets. Higher associativity usually increases the cache hit
  rate and thereby the performance. The downside is higher power
  consumption and increased gate-count for tag comparators.

  Note that a 1-set cache is effectively a direct-mapped cache.

Data cache set size
CONFIG_DCACHE_SZ1
  The size of each set in the data cache (kbytes). Valid values are
  1 - 64 in binary steps. Note that the full range is only supported
  by the generic and virtex2 targets. Most target packages are limited
  to 2 - 16 kbyte. A large cache gives higher performance but the
  data cache is timing critical an a too large setting might affect
  the maximum frequency (on ASIC targets). The total data cache size
  is the number of set multiplied with the set size.

Data cache line size
CONFIG_DCACHE_LZ16
  The data cache line size. Can be set to either 16 or 32 bytes per
  line. A smaller line size gives better associativity and higher
  cache hit rate, but requires a larger tag memory.

Data cache replacement algorithm
CONFIG_DCACHE_ALGORND
  See the explanation for instruction cache replacement algorithm.

Data cache locking
CONFIG_DCACHE_LOCK
  Say Y here to enable cache locking in the data cache.
  Locking can be done on cache-line level, but will increase the
  width of the tag ram with one bit. If you don't know what
  locking is good for, it is safe to say N.

Data cache snooping
CONFIG_DCACHE_SNOOP
  Say Y here to enable data cache snooping on the AHB bus. Is only
  useful if you have additional AHB masters such as the DSU or a
  target PCI interface. Note that the target technology must support
  dual-port RAMs for this option to be enabled. Dual-port RAMS are
  currently supported on Virtex/2, Virage and Actel targets.

Data cache snooping implementation
CONFIG_DCACHE_SNOOP_FAST
  The default snooping implementation is 'slow', which works if you 
  don't have AHB slaves in cacheable areas capable of zero-waitstates 
  non-sequential write accesses. Otherwise use 'fast' and suffer a 
  few kgates extra area. This option is currently only needed in
  multi-master systems with the SSRAM or DDR memory controllers.

Fixed cacheability map
CONFIG_CACHE_FIXED
  If this variable is 0, the cacheable memory regions are defined
  by the AHB plug&play information (default). To overriden the
  plug&play settings, this variable can be set to indicate which
  areas should be cached. The value is treated as a 16-bit hex value
  with each bit defining if a 256 Mbyte segment should be cached or not.
  The right-most (LSB) bit defines the cacheability of AHB address
  0 - 256 MByte, while the left-most bit (MSB) defines AHB address
  3840 - 4096 MByte. If the bit is set, the corresponding area is
  cacheable. A value of 00F3 defines address 0 - 0x20000000 and
  0x40000000 - 0x80000000 as cacheable.

Local data ram
CONFIG_DCACHE_LRAM
  Say Y here to add a local ram to the data cache controller.
  Accesses to the ram (load/store) will be performed at 0 waitstates
  and store data will never be written back to the AHB bus.

Size of local data ram
CONFIG_DCACHE_LRAM_SZ1
  Defines the size of the local data ram in Kbytes. Note that most
  technology libraries do not support larger rams than 16 Kbyte.

Start address of local data ram
CONFIG_DCACHE_LRSTART
  Defines the 8 MSB bits of start address of the local data ram.
  By default set to 8f (start address = 0x8f000000), but any value
  (except 0) is possible. Note that the local data ram 'shadows'
  a 16 Mbyte block of the address space.

MMU enable
CONFIG_MMU_ENABLE
  Say Y here to enable the Memory Management Unit.

MMU split icache/dcache table lookaside buffer
CONFIG_MMU_COMBINED
  Select "combined" for a combined icache/dcache table lookaside buffer,
  "split" for a split icache/dcache table lookaside buffer

MMU tlb replacement scheme
CONFIG_MMU_REPARRAY
  Select "LRU" to use the "least recently used" algorithm for TLB
  replacement, or "Increment" for a simple incremental replacement
  scheme.

Combined i/dcache tlb
CONFIG_MMU_I2
  Select the number of entries for the instruction TLB, or the
  combined icache/dcache TLB if such is used.

Split tlb, dcache
CONFIG_MMU_D2
  Select the number of entries for the dcache TLB.

mmu snooping
CONFIG_DCACHE_MMUSNOOP
  Save physical tags along with virtual tags. This is
  needed on smp systems with MMU enabled. Adds extra
  RAM to store the physical address beside the 
  simple snoopings dualport ram. If disabled
  snooping will only work with MMU disabled.

DSU enable
CONFIG_DSU_ENABLE
  The debug support unit (DSU) allows non-intrusive debugging and tracing
  of both executed instructions and AHB transfers. If you want to enable
  the DSU, say Y here and select the configuration below.

Trace buffer enable
CONFIG_DSU_TRACEBUF
  Say Y to enable the trace buffer. The buffer is not necessary for
  debugging, only for tracing instructions and data transfers.

Enable instruction tracing
CONFIG_DSU_ITRACE
  If you say Y here, an instruction trace buffer will be implemented
  in each processor. The trace buffer will trace executed instructions
  and their results, and place them in a circular buffer. The buffer 
  can be read out by any AHB master, and in particular by the debug 
  communication link.

Size of trace buffer
CONFIG_DSU_ITRACESZ1
  Select the buffer size (in kbytes) for the instruction trace buffer. 
  Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
  need 2 kbyte.

Enable AHB tracing
CONFIG_DSU_ATRACE
  If you say Y here, an AHB trace buffer will be implemented in the
  debug support unit processor. The AHB buffer will trace all transfers
  on the AHB bus and save them in a circular buffer. The trace buffer 
  can be read out by any AHB master, and in particular by the debug 
  communication link.

Size of trace buffer
CONFIG_DSU_ATRACESZ1
  Select the buffer size (in kbytes) for the AHB trace buffer. 
  Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
  need 2 kbyte.


IU assembly printing
CONFIG_IU_DISAS
  Enable printing of executed instructions to the console.

IU assembly printing in netlist
CONFIG_IU_DISAS_NET
  Enable printing of executed instructions to the console also
  when simulating a netlist. NOTE: with this option enabled, it
  will not be possible to pass place&route.

32-bit program counters
CONFIG_DEBUG_PC32
  Since the LSB 2 bits of the program counters always are zero, they are
  normally not implemented. If you say Y here, the program counters will
  be implemented with full 32 bits, making debugging of the VHDL model
  much easier. Turn of this option for synthesis or you will be wasting
  area.

CONFIG_AHB_DEFMST
  Sets the default AHB master (see AMBA 2.0 specification for definition).
  Should not be set to a value larger than the number of AHB masters - 1.
  For highest processor performance, leave it at 0.

Default AHB master
CONFIG_AHB_RROBIN
  Say Y here to enable round-robin arbitration of the AHB bus. A N will
  select fixed priority, with the master with the highest bus index having
  the highest priority.

Support AHB split-transactions
CONFIG_AHB_SPLIT
  Say Y here to enable AHB split-transaction support in the AHB arbiter.
  Unless you actually have an AHB slave that can generate AHB split
  responses, say N and save some gates.

Default AHB master
CONFIG_AHB_IOADDR
  Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined 
  in the plug&play extentions of the AMBA bus. Should be kept to FFF 
  unless you really know what you are doing.

APB bridge address          
CONFIG_APB_HADDR
  Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be
  kept at 800 for software compatibility. 


DSU enable
CONFIG_DSU_UART
  Say Y to enable the AHB uart (serial-to-AHB). This is the most
  commonly used debug communication link.

JTAG Enable
CONFIG_DSU_JTAG
  Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done 
  with GRMON through the boards JTAG chain at speed of 300 kbits/s. 
  Supported JTAG cables are Xilinx Parallel Cable III and IV.  

Ethernet DSU enable
CONFIG_DSU_ETH
  Say Y to enable the Ethernet Debug Communication Link (EDCL). The link
  provides a DSU gateway between ethernet and the AHB bus. Debugging is
  done at 10 or 100 Mbit/s, using the GRMON debug monitor. You must
  enable the GRETH Ethernet MAC for this option to become active.

Size of EDCL trace buffer
CONFIG_DSU_ETHSZ1
  Select the buffer size (in kbytes) for the EDCL. 1 or 2 kbyte is
  usually enough, while a larger buffer will increase the transfer rate.
  When operating at 100 Mbit, use a buffer size of at least 8 kbyte for
  maximum throughput.

MSB IP address
CONFIG_DSU_IPMSB
  Set the MSB 16 bits of the IP address of the EDCL.

LSB IP address
CONFIG_DSU_IPLSB
  Set the LSB 16 bits of the IP address of the EDCL.

MSB ethernet address
CONFIG_DSU_ETHMSB
  Set the MSB 24 bits of the ethernet address of the EDCL.

LSB ethernet address
CONFIG_DSU_ETHLSB
  Set the LSB 24 bits of the ethernet address of the EDCL.
Leon2 memory controller
CONFIG_MCTRL_LEON2
  Say Y here to enable the LEON2 memory controller. The controller
  can access PROM, I/O, SRAM and SDRAM. The bus width for PROM
  and SRAM is programmable to 8-, 16- or 32-bits.

8-bit memory support
CONFIG_MCTRL_8BIT
  If you say Y here, the PROM/SRAM memory controller will support
  8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit.
  Say N to save a few hundred gates.