config.help

LEON3 SOC GRlip IP core. Memory controller.

Prompt for target technology
CONFIG_SYN_INFERRED
  Selects the target technology for memory and pads. 
  The following are available:

  - Inferred: Generic FPGA or ASIC targets if your synthesis tool
    is capable of inferring RAMs and pads automatically.

  - Actel ProAsic/P/3 and Axellerator FPGAs
  - Altera: Any Altera FPGA family           
  - ATC18: Atmel-Nantes 0.18 um rad-hard CMOS
  - IHP25: IHP 0.25 um CMOS
  - Lattice : EC/ECP/XP FPGAs
  - UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries
  - Xilinx-Spartan/2/3: Xilinx Spartan/2/3 libraries
  - Xilinx-Spartan3E: Xilinx Spartan3E libraries
  - Xilinx-Virtex/E: Xilinx Virtex/E libraries
  - Xilinx-Virtex2/4/5: Xilinx Virtex2/4/5 libraries


Ram library
CONFIG_MEM_VIRAGE
  Select RAM generators for ASIC targets. 

Infer ram
CONFIG_SYN_INFER_RAM
  Say Y here if you want the synthesis tool to infer your
  RAM automatically. Say N to directly instantiate technology-
  specific RAM cells for the selected target technology package.

Infer pads
CONFIG_SYN_INFER_PADS
  Say Y here if you want the synthesis tool to infer pads.
  Say N to directly instantiate technology-specific pads from
  the selected target technology package.

No async reset
CONFIG_SYN_NO_ASYNC
  Say Y here if you disable asynchronous reset in some of the IP cores.
  Might be necessary if the target library does not have cells with
  asynchronous set/reset.


Use Virtex CLKDLL for clock synchronisation
CONFIG_CLK_INFERRED
  Certain target technologies include clock generators to scale or
  phase-adjust the system and SDRAM clocks. This is currently supported
  for Xilinx and Altera FPGAs. Depending on technology, you can select
  to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2), the
  Xilinx DCM (Virtex-2, Spartan3, Virtex-4), or the Altera ALTDLL
  (Stratix, Cyclone). Choose the 'inferred' option if you are not
  using Xilinx or Altera FPGAs.

  Using a technology specific clock generator is necessary to
  re-syncronize the SDRAM clock. For this to work, connect the
  external SDCLK signal with PLLREF. 

Clock multiplier
CONFIG_CLK_MUL
  When using the Xilinx DCM or Altera ALTPLL, the system clock can
  be multiplied with a factor of 2 - 32, and divided by a factor of
  1 - 32. This makes it possible to generate almost any desired 
  processor frequency. When using the Xilinx CLKDLL generator,
  the resulting frequency scale factor (mul/div) must be one of
  1/2, 1 or 2.

  WARNING: The resulting clock must be within the limits specified
  by the target FPGA family.

Clock divider
CONFIG_CLK_DIV
  When using the Xilinx DCM or Altera ALTPLL, the system clock can
  be multiplied with a factor of 2 - 32, and divided by a factor of
  1 - 32. This makes it possible to generate almost any desired 
  processor frequency. When using the Xilinx CLKDLL generator,
  the resulting frequency scale factor (mul/div) must be one of
  1/2, 1 or 2.

  WARNING: The resulting clock must be within the limits specified
  by the target FPGA family.

System clock multiplier
CONFIG_CLKDLL_1_2
  The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0, 
  or 2.0. Useful when the target board has an oscillator with a too high 
  (or low) frequency for your design. The divided clock will be used as the
  main clock for the whole processor (except PCI and ethernet clocks).

System clock multiplier
CONFIG_DCM_2_3
  The Xilinx DCM and Altera ALTDLL can scale the input clock with a large
  range of factors. Useful when the target board has an oscillator with a 
  too high (or low) frequency for your design. The divided clock will
  be used as the main clock for the whole processor (except PCI and 
  ethernet clocks). NOTE: the resulting frequency must be at least
  24 MHz or the DCM and ALTDLL might not work.

Enable CLKDLL for PCI clock
CONFIG_PCI_CLKDLL
  Say Y here to re-synchronize the PCI clock using a 
  Virtex BUFGDLL macro. Will improve PCI clock-to-output 
  delays on the expense of input-setup requirements.

Use PCI clock system clock
CONFIG_PCI_SYSCLK
  Say Y here to the PCI clock to generate the system clock.
  The PCI clock can be scaled using the DCM or CLKDLL to 
  generate a suitable processor clock.

External SDRAM clock feedback
CONFIG_CLK_NOFB
  Say Y here to disable the external clock feedback to synchronize the
  SDRAM clock. This option is necessary if your board or design does not
  have an external clock feedback that is connected to the pllref input
  of the clock generator.
Number of processors
CONFIG_PROC_NUM
  The number of processor cores. The LEON3MP design can accomodate
  up to 4 LEON3 processor cores. Use 1 unless you know what you are
  doing ...

Number of SPARC register windows
CONFIG_IU_NWINDOWS
  The SPARC architecture (and LEON) allows 2 - 32 register windows.
  However, any number except 8 will require that you modify and 
  recompile your run-time system or kernel. Unless you know what
  you are doing, use 8.

SPARC V8 multiply and divide instruction
CONFIG_IU_V8MULDIV
  If you say Y here, the SPARC V8 multiply and divide instructions
  will be implemented. The instructions are: UMUL, UMULCC, SMUL,
  SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent
  integer multiplications and divisions, significant performance
  increase can be achieved. Emulated floating-point operations will
  also benefit from this option.

  By default, the gcc compiler does not emit multiply or divide
  instructions and your code must be compiled with -mv8 to see any
  performance increase. On the other hand, code compiled with -mv8
  will generate an illegal instruction trap when executed on processors
  with this option disabled.

  The divider consumes approximately 2 kgates, the multiplier 6 kgates.

Multiplier latency
CONFIG_IU_MUL_LATENCY_4
  The multiplier used for UMUL/SMUL instructions is implemented
  with a 16x16 multiplier which is iterated 4 times. This leads
  to a 4-cycle latency for multiply operations. To improve timing,
  a pipeline stage can be inserted into the 16x16 multiplier which
  will lead to a 5-cycle latency for the multiply oprations.

Multiplier latency
CONFIG_IU_MUL_MAC
  If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate)
  instructions will be enabled. The instructions implement a
  single-cycle 16x16->32 bits multiply with a 40-bits accumulator.
  The details of these instructions can be found in the LEON manual,

Single vector trapping
CONFIG_IU_SVT
  Single-vector trapping is a SPARC V8e option to reduce code-size
  in small applications. If enabled, the processor will jump to 
  the address of trap 0 (tt = 0x00) for all traps. No trap table
  is then needed. The trap type is present in %psr.tt and must
  be decoded by the O/S. Saves 4 Kbyte of code, but increases
  trap and interrupt overhead. Currently, the only O/S supporting
  this option is eCos. To enable SVT, the O/S must also set bit 13
  in %asr17.

Load latency
CONFIG_IU_LDELAY
  Defines the pipeline load delay (= pipeline cycles before the data
  from a load instruction is available for the next instruction).
  One cycle gives best performance, but might create a critical path
  on targets with slow (data) cache memories. A 2-cycle delay can
  improve timing but will reduce performance with about 5%.

Reset address
CONFIG_IU_RSTADDR
  By default, a SPARC processor starts execution at address 0.
  With this option, any 4-kbyte aligned reset start address can be
  choosen. Keep at 0 unless you really know what you are doing.

Power-down
CONFIG_PWD
  Say Y here to enable the power-down feature of the processor.
  Might reduce the maximum frequency slightly on FPGA targets.
  For details on the power-down operation, see the LEON3 manual.

Hardware watchpoints
CONFIG_IU_WATCHPOINTS
  The processor can have up to 4 hardware watchpoints, allowing to 
  create both data and instruction breakpoints at any memory location,
  also in PROM. Each watchpoint will use approximately 500 gates.
  Use 0 to disable the watchpoint function.

Floating-point enable
CONFIG_FPU_ENABLE
  Say Y here to enable the floating-point interface for the MEIKO
  or GRFPU. Note that no FPU's are provided with the GPL version
  of GRLIB. Both the Gaisler GRFPU and the Meiko FPU are commercial 
  cores and must be obtained separately. 

FPU selection
CONFIG_FPU_GRFPU
  Select between Gaisler Research's GRFPU and GRFPU-lite FPUs or the Sun 
  Meiko FPU core. All cores  are fully IEEE-754 compatible and support
  all SPARC FPU instructions.

GRFPU Multiplier
CONFIG_FPU_GRFPU_INFMUL
  On FPGA targets choose inferred multiplier. For ASIC implementations 
  choose between Synopsys Design Ware (DW) multiplier or Module 
  Generator (ModGen) multiplier. DW multiplier gives better results 
  (smaller area  and better timing) but requires DW license. ModGen 
  multiplier is part of GRLIB and does not require license. 

GRFPC Configuration
CONFIG_FPU_GRFPC0
  Configures the GRFPU-LITE controller. 

  In simple configuration controller executes FP instructions 
  in parallel with  integer instructions. FP operands are fetched 
  in the register file stage and the result is written in the write 
  stage. This option uses least area resources.

  Data forwarding configuration gives ~ 10 % higher FP performance than 
  the simple configuration by adding data forwarding between the pipeline
  stages. 

  Non-blocking controller allows FP load and store instructions to
  execute in parallel with FP instructions. The performance increase is 
  ~ 20 % for FP applications. This option uses most logic resources and 
  is suitable for ASIC implementations. 

Enable Instruction cache
CONFIG_ICACHE_ENABLE
  The instruction cache should always be enabled to allow
  maximum performance. Some low-end system might want to
  save area and disable the cache, but this will reduce
  the performance with a factor of 2 - 3.

Enable Data cache
CONFIG_DCACHE_ENABLE
  The data cache should always be enabled to allow
  maximum performance. Some low-end system might want to
  save area and disable the cache, but this will reduce
  the performance with a factor of 2 at least.

Instruction cache associativity
CONFIG_ICACHE_ASSO1
  The instruction cache can be implemented as a multi-set cache with
  1 - 4 sets. Higher associativity usually increases the cache hit
  rate and thereby the performance. The downside is higher power
  consumption and increased gate-count for tag comparators.

  Note that a 1-set cache is effectively a direct-mapped cache.

Instruction cache set size
CONFIG_ICACHE_SZ1
  The size of each set in the instuction cache (kbytes). Valid values
  are 1 - 64 in binary steps. Note that the full range is only supported
  by the generic and virtex2 targets. Most target packages are limited
  to 2 - 16 kbyte. Large set size gives higher performance but might
  affect the maximum frequency (on ASIC targets). The total instruction
  cache size is the number of set multiplied with the set size.

Instruction cache line size
CONFIG_ICACHE_LZ16
  The instruction cache line size. Can be set to either 16 or 32
  bytes per line. Instruction caches typically benefit from larger
  line sizes, but on small caches it migh be better with 16 bytes/line
  to limit eviction miss rate.