readme.txt

来自「The GRLIB IP Library is an integrated se」· 文本 代码 · 共 26 行

This leon3 design is tailored to the Altera NiosII Startix2 
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. 

As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written. 

NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.


* How to program the flash prom with a FPGA programming file

  1. Create a hex file of the programming file with Quartus.

  2. Convert it to srecord and adjust the load address:

	objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec

  3. Program the flash memory using grmon:

      flash erase 0x800000 0xb00000
      flash load fpga.srec