platform.s

AT91所有开发板的资料 AT91所有开发板的资料

;/*****************************************************************************
; * Copyright (C) ARM Limited 1998. All rights reserved. 
; *****************************************************************************/
;/************************************************************************
;
;  EVALUATOR7T address map
;
;	NOTE: This is a multi-hosted header file for use with uHAL and
;	      supported debuggers.
;
;************************************************************************/

 IF :LNOT: :DEF: __address_h
__address_h		EQU	1

PLATFORM_ID		EQU	0x0062A

; Common modules for uHAL can be included or excluded by changing these
; definitions. These can be over-ridden by the makefile/ARM project file
; provided the .h file can is rebuilt.
 IF :LNOT: :DEF: uHAL_BOOT
uHAL_BOOT		EQU	0
 ENDIF
 IF :LNOT: :DEF: uHAL_TIMERS
uHAL_TIMERS		EQU	1
 ENDIF
 IF :LNOT: :DEF: uHAL_INTERRUPTS
uHAL_INTERRUPTS		EQU	1
 ENDIF
 IF :LNOT: :DEF: uHAL_COMPLEX_IRQ
uHAL_COMPLEX_IRQ	EQU	1
 ENDIF
 IF :LNOT: :DEF: uHAL_PCI
uHAL_PCI		EQU	0
 ENDIF
 IF :LNOT: :DEF: uHAL_HEAP
uHAL_HEAP_BASE			EQU	(SZ_256K + SZ_64K)
uHAL_HEAP_SIZE			EQU	(SZ_256K - SZ_32K)
uHAL_HEAP		EQU	1
 ENDIF

; /* memory size */
; EVALUATOR7T has been fitted with 512K bytes of SRAM
uHAL_MEMORY_SIZE	EQU	(SZ_512K)
EVALUATOR_SSRAM_BASE	EQU	(0)
EVALUATOR_SSRAM_SIZE	EQU	(SZ_512K)
EVALUATOR_FLASH_BASE	EQU	(0x01800000)
EVALUATOR_FLASH_SIZE	EQU	(SZ_512K)

; System Manager Group
SYSCFG		EQU	0x03FF0000
EXTDBWTH	EQU	(SYSCFG + 0x3010)
ROMCON1		EQU	(SYSCFG + 0x3018)

; Interrupt Controller Group
INTMOD		EQU	(SYSCFG + 0x4000)
INTPND		EQU	(SYSCFG + 0x4004)
INTMSK		EQU	(SYSCFG + 0x4008)

MAXIRQNUM	EQU	21
MAXFIQNUM	EQU	21
MAXSWINUM	EQU	15

NR_IRQS		EQU	(MAXIRQNUM + 1)

INT_TIMER0	EQU	(10)
INT_TIMER1	EQU	(11)
INT_GLOBAL	EQU	(21)

INT_UART0_TX	EQU	(4)
INT_UART0_RX	EQU	(5)
INT_UART1_TX	EQU	(6)
INT_UART1_RX	EQU	(7)

INT_UART1_TX_MASK	EQU (1 << INT_UART1_TX )
INT_UART1_RX_MASK	EQU (1 << INT_UART1_RX )

; /* Timer stuff */
OS_TIMER	EQU	1
MAX_TIMER	EQU	2

; The irq numbers of the individual timers
;#define TIMER_VECTORS	{ 0, INT_TIMER0, INT_TIMER1 }

; Timer Registers
TMOD		EQU	(SYSCFG + 0x6000)
TDATA0		EQU	(SYSCFG + 0x6004)
TDATA1		EQU	(SYSCFG + 0x6008)

; Timer Mode Register bits
TMR_TE0		EQU	(1<<0)
TMR_TMD0	EQU	(1<<1)
TMR_TCLR0	EQU	(1<<2)
TMR_TE1		EQU	(1<<3)
TMR_TMD1	EQU	(1<<4)
TMR_TCLR1	EQU	(1<<5)


; 50 MHz clock => 50,000 ticks / mSec
; Max period is a bit larger than 85 s
mSEC_1			EQU	(0xC350)
MAX_PERIOD		EQU	(0xFFFFFFFF)

; /* LEDs */
; LEDs are accessed through the I/O Port
; I/O Ports
IOPMOD		EQU	(SYSCFG + 0x5000)
IOPCON		EQU	(SYSCFG + 0x5004)
IOPDATA		EQU	(SYSCFG + 0x5008)

LED_BANK	EQU	IOPDATA
ALL_LEDS	EQU	0xF0

uHAL_NUM_OF_LEDS	EQU	4

;#define uHAL_LED_MASKS	{ 0, 16, 32, 64, 128 }
;#define uHAL_LED_OFFSETS { 0, (void *)LED_BANK,(void *)LED_BANK,(void *)LED_BANK,(void *)LED_BANK }
 IF :LNOT: :DEF: HIGH
HIGH			EQU	1
 ENDIF
uHAL_LED_ON		EQU	1
uHAL_LED_OFF		EQU	0

; /* UART */
UART0_BASE	EQU	(SYSCFG + 0xD000)
UART1_BASE	EQU	(SYSCFG + 0xE000)
	
ULCON	EQU	0x00
UCON	EQU	0x04
USTAT	EQU	0x08
UTXBUF	EQU	0x0C
URXBUF	EQU	0x10
UBRDIV	EQU	0x14

;/*
; * Line Control Register bits
; */
ULCR8bits	EQU	(3)
ULCRS1StopBit	EQU	(0)
ULCRNoParity	EQU	(0)

;/*
; * UART Control Register bits
; */
UCRRxM	EQU	(1)
UCRRxSI	EQU	(1 << 2)
UCRTxM	EQU	(1 << 3)
UCRLPB	EQU	(1 << 7)


;/*
; * UART Status Register bits
; */
USROverrun      EQU	(1 << 0)
USRParity       EQU	(1 << 1)
USRFraming      EQU	(1 << 2)
USRBreak        EQU	(1 << 3)
USRDTR		EQU	(1 << 4)
USRRxData       EQU	(1 << 5)
USRTxHoldEmpty  EQU	(1 << 6)
USRTxEmpty      EQU	(1 << 7)


; /* define it so that it only ever uses one port */
HOST_COMPORT		EQU	UART1_BASE
SEMIHOSTED_COMPORT	EQU	HOST_COMPORT
OS_COMPORT		EQU	HOST_COMPORT

; /* default baud rate value */
BAUD_9600	  EQU  (162 << 4)
DEFAULT_OS_BAUD	  EQU  BAUD_9600

; UART registers are on word aligned, D8
; See lib/uart.c

; Beware of side effects with IO_MAPADDRESS
;#define IO_MAPADDRESS(a)	(((0xFF & (unsigned int) (a)) << 2) | (0xFFFFFF00 & (unsigned int) (a)))
;#define _MapAddress(a)		IO_MAPADDRESS(a)
;#define IO_READ(p)		(*(unsigned  *)(IO_MAPADDRESS(p)))
;#define IO_WRITE(p, c)		(*(unsigned  *)(IO_MAPADDRESS(p)) = c)

;/* UART primitives */
;#define GET_STATUS(p)	(*(volatile unsigned  *)((p) + USTAT))
;#define RX_DATA(s)     ((s) & USRRxData)
;#define GET_CHAR(p)	(*(volatile unsigned  *)((p) + URXBUF))
;#define TX_READY(s)    ((s) & USRTxHoldEmpty)
;#define PUT_CHAR(p,c)  (*(unsigned  *)((p) + UTXBUF) = (unsigned )(c))
		
;/*************************************************************************/
;/*  SYSTEM MEMORY CONTROL REGISTER EQU TABLES                            */
;/*************************************************************************/

fMCLK_MHz	EQU	50000000   ; 50MHz, KS32C50100 default
MHz		EQU     1000000
fMCLK		EQU     (fMCLK_MHz/MHz)

;/* -> EXTDBWTH : Memory Bus Width register */
;-------------------------------------------------------------
;
DSR0  		EQU  2:SHL:0           ; ROM0	Flash		 0 : Disable
				       ;       			 1 : Byte
				       ;       			 2 : Half-Word
				       ;       			 3 : Word
DSR1  		EQU  3:SHL:2           ; ROM1	SRAM
DSR2  		EQU  3:SHL:4           ; ROM2	SRAM
DSR3  		EQU  0:SHL:6           ; ROM3
DSR4  		EQU  0:SHL:8           ; ROM4
DSR5  		EQU  0:SHL:10          ; ROM5
DSD0  		EQU  0:SHL:12          ; DRAM0
DSD1  		EQU  0:SHL:14          ; DRAM1
DSD2  		EQU  0:SHL:16          ; DRAM2
DSD3  		EQU  0:SHL:18          ; DRAM3
DSX0  		EQU  0:SHL:20          ; EXTIO0
DSX1  		EQU  0:SHL:22          ; EXTIO1
DSX2  		EQU  0:SHL:24          ; EXTIO2
DSX3  		EQU  0:SHL:26          ; EXTIO3

rEXTDBWTH   EQU  DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3
;-------------------------------------------------------------

;/* -> ROMCON0 : ROM Bank0 Control register */
;-------------------------------------------------------------
ROMBasePtr0     EQU  0x180:SHL:10   ;=0x1800000  
ROMEndPtr0      EQU  0x188:SHL:20   ;=0x1880000  
PMC0            EQU  0x0            ; 0x0=Normal ROM, 0x1=4Word Page 
                                    ; 0x2=8Word Page, 0x3=16Word Page
rTpa0           EQU  (0x0:SHL:2)    ; 0x0=5Cycle, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle 
rTacc0          EQU  (0x3:SHL:4)    ; 0x0=Disable, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle
                                    ; 0x4=5Cycle, 0x5=6Cycle
                                    ; 0x6=7Cycle, 0x7=Reserved
rROMCON0   EQU  ROMEndPtr0+ROMBasePtr0+rTacc0+rTpa0+PMC0
;-------------------------------------------------------------


;/* -> ROMCON1 : ROM Bank1 Control register */
;-------------------------------------------------------------
ROMBasePtr1     EQU  0x000:SHL:10   ;=0x0000000  
ROMEndPtr1      EQU  0x004:SHL:20   ;=0x0040000  
PMC1            EQU  0x0            ; 0x0=Normal ROM, 0x1=4Word Page 
                                    ; 0x2=8Word Page, 0x3=16Word Page
rTpa1           EQU  (0x0:SHL:2)    ; 0x0=5Cycle, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle 
rTacc1          EQU  (0x1:SHL:4)    ; 0x0=Disable, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle
                                    ; 0x4=5Cycle, 0x5=6Cycle
                                    ; 0x6=7Cycle, 0x7=Reserved
rROMCON1   EQU  ROMEndPtr1+ROMBasePtr1+rTacc1+rTpa1+PMC1
;-------------------------------------------------------------

;/* -> ROMCON2 : ROM Bank2 Control register */
;-------------------------------------------------------------
ROMBasePtr2     EQU  0x004:SHL:10   ;=0x0040000  
ROMEndPtr2      EQU  0x008:SHL:20   ;=0x0080000  
PMC2            EQU  0x0            ; 0x0=Normal ROM, 0x1=4Word Page 
                                    ; 0x2=8Word Page, 0x3=16Word Page
rTpa2           EQU  (0x0:SHL:2)    ; 0x0=5Cycle, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle 
rTacc2          EQU  (0x1:SHL:4)    ; 0x0=Disable, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle
                                    ; 0x4=5Cycle, 0x5=6Cycle
                                    ; 0x6=7Cycle, 0x7=Reserved
rROMCON2   EQU  ROMEndPtr2+ROMBasePtr2+rTacc2+rTpa2+PMC2
;-------------------------------------------------------------

;/* -> ROMCON3 : ROM Bank3 Control register */
;-------------------------------------------------------------
ROMBasePtr3     EQU  0x060:SHL:10   ;=0x0600000  
ROMEndPtr3      EQU  0x080:SHL:20   ;=0x0800000  
PMC3            EQU  0x0            ; 0x0=Normal ROM, 0x1=4Word Page 
                                    ; 0x2=8Word Page, 0x3=16Word Page
rTpa3           EQU  (0x0:SHL:2)    ; 0x0=5Cycle, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle 
rTacc3          EQU  (0x2:SHL:4)    ; 0x0=Disable, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle
                                    ; 0x4=5Cycle, 0x5=6Cycle
                                    ; 0x6=7Cycle, 0x7=Reserved
rROMCON3   EQU  ROMEndPtr3+ROMBasePtr3+rTacc3+rTpa3+PMC3
;-------------------------------------------------------------

;/* -> ROMCON4 : ROM Bank4 Control register */
;-------------------------------------------------------------
ROMBasePtr4     EQU  0x080:SHL:10   ;=0x0800000  
ROMEndPtr4      EQU  0x0A0:SHL:20   ;=0x0A00000  
PMC4            EQU  0x0            ; 0x0=Normal ROM, 0x1=4Word Page 
                                    ; 0x2=8Word Page, 0x3=16Word Page
rTpa4           EQU  (0x0:SHL:2)    ; 0x0=5Cycle, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle 
rTacc4          EQU  (0x4:SHL:4)    ; 0x0=Disable, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle
                                    ; 0x4=5Cycle, 0x5=6Cycle
                                    ; 0x6=7Cycle, 0x7=Reserved
rROMCON4   EQU  ROMEndPtr4+ROMBasePtr4+rTacc4+rTpa4+PMC4
;-------------------------------------------------------------

;/* -> ROMCON5 : ROM Bank5 Control register */
;-------------------------------------------------------------
ROMBasePtr5     EQU  0x0A0:SHL:10   ;=0x0A00000  
ROMEndPtr5      EQU  0x0C0:SHL:20   ;=0x0C00000  
PMC5            EQU  0x0            ; 0x0=Normal ROM, 0x1=4Word Page 
                                    ; 0x2=8Word Page, 0x3=16Word Page
rTpa5           EQU  (0x0:SHL:2)    ; 0x0=5Cycle, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle 
rTacc5          EQU  (0x4:SHL:4)    ; 0x0=Disable, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle
                                    ; 0x4=5Cycle, 0x5=6Cycle
                                    ; 0x6=7Cycle, 0x7=Reserved
rROMCON5   EQU  ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC5
;-------------------------------------------------------------

;/* -> DRAMCON0 : RAM Bank0 control register */
rDRAMCON0   EQU  0
rSDRAMCON0	    EQU	 0
;-------------------------------------------------------------

;/* -> DRAMCON1 : RAM Bank1 control register */
rDRAMCON1   EQU  0
rSDRAMCON1			EQU	 0
;-------------------------------------------------------------

;/* -> DRAMCON2 : RAM Bank2 control register */
rDRAMCON2   EQU  0
rSDRAMCON2			EQU	 0
;-------------------------------------------------------------

;/* -> DRAMCON3 : RAM Bank3 control register */
rDRAMCON3   EQU  0
rSDRAMCON3			EQU	 0
;-------------------------------------------------------------

;/* -> REFEXTCON : External I/O & Memory Refresh cycle Control Register */
;-------------------------------------------------------------
RefCycle        EQU   16   ;Unit [us], 1k refresh 16ms
;RefCycle        EQU   8   ;Unit [us], 1k refresh 16ms
CASSetupTime    EQU   0    ;0=1cycle, 1=2cycle
CASHoldTime     EQU   0    ;0=1cycle, 1=2cycle, 2=3cycle,
                           ;3=4cycle, 4=5cycle,
RefCycleValue   EQU   ((2048+1-(RefCycle*fMCLK)):SHL:21)
Tcsr            EQU   (CASSetupTime:SHL:20)   ; 1cycle
Tcs             EQU   (CASHoldTime:SHL:17)    
ExtIOBase       EQU   0x18360      ; Refresh enable, VSF=1
;
rREFEXTCON      EQU   RefCycleValue+Tcsr+Tcs+ExtIOBase
;-------------------------------------------------------------
;SRefCycle       EQU   16   ;Unit [us], 4k refresh 64ms
SRefCycle       EQU   8   ;Unit [us], 4k refresh 64ms
ROWcycleTime    EQU   3    ;0=1cycle, 1=2cycle, 2=3cycle,
                           ;3=4cycle, 4=5cycle,
SRefCycleValue  EQU   ((2048+1-(SRefCycle*fMCLK)):SHL:21)
STrc            EQU   (ROWcycleTime:SHL:17)    
rSREFEXTCON     EQU   SRefCycleValue+STrc+ExtIOBase
;-------------------------------------------------------------


 ENDIF

	END