platform.h

AT91所有开发板的资料 AT91所有开发板的资料

#define fMCLK                           (fMCLK_MHz/MHz)

/* -> EXTDBWTH : Memory Bus Width register */
/* -------------------------------------------------------------
 * 
 */
#define DSR0                            2:SHL:0            /*  ROM0	Flash		 0 : Disable */
/*        			 1 : Byte
 *        			 2 : Half-Word
 *        			 3 : Word
 */
#define DSR1                            3:SHL:2            /*  ROM1	SRAM */
#define DSR2                            3:SHL:4            /*  ROM2	SRAM */
#define DSR3                            0:SHL:6            /*  ROM3 */
#define DSR4                            0:SHL:8            /*  ROM4 */
#define DSR5                            0:SHL:10           /*  ROM5 */
#define DSD0                            0:SHL:12           /*  DRAM0 */
#define DSD1                            0:SHL:14           /*  DRAM1 */
#define DSD2                            0:SHL:16           /*  DRAM2 */
#define DSD3                            0:SHL:18           /*  DRAM3 */
#define DSX0                            0:SHL:20           /*  EXTIO0 */
#define DSX1                            0:SHL:22           /*  EXTIO1 */
#define DSX2                            0:SHL:24           /*  EXTIO2 */
#define DSX3                            0:SHL:26           /*  EXTIO3 */

#define rEXTDBWTH                       DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3
/* -------------------------------------------------------------
 */

/* -> ROMCON0 : ROM Bank0 Control register */
/* -------------------------------------------------------------
 */
#define ROMBasePtr0                     0x180:SHL:10    /* =0x1800000   */
#define ROMEndPtr0                      0x188:SHL:20    /* =0x1880000   */
#define PMC0                            0x0             /*  0x0=Normal ROM, 0x1=4Word Page  */
/*  0x2=8Word Page, 0x3=16Word Page
 */
#define rTpa0                           (0x0:SHL:2)     /*  0x0=5Cycle, 0x1=2Cycle */
/*  0x2=3Cycle, 0x3=4Cycle 
 */
#define rTacc0                          (0x3:SHL:4)     /*  0x0=Disable, 0x1=2Cycle */
/*  0x2=3Cycle, 0x3=4Cycle
 *  0x4=5Cycle, 0x5=6Cycle
 *  0x6=7Cycle, 0x7=Reserved
 */
#define rROMCON0                        ROMEndPtr0+ROMBasePtr0+rTacc0+rTpa0+PMC0
/* -------------------------------------------------------------
 */


/* -> ROMCON1 : ROM Bank1 Control register */
/* -------------------------------------------------------------
 */
#define ROMBasePtr1                     0x000:SHL:10    /* =0x0000000   */
#define ROMEndPtr1                      0x004:SHL:20    /* =0x0040000   */
#define PMC1                            0x0             /*  0x0=Normal ROM, 0x1=4Word Page  */
/*  0x2=8Word Page, 0x3=16Word Page
 */
#define rTpa1                           (0x0:SHL:2)     /*  0x0=5Cycle, 0x1=2Cycle */
/*  0x2=3Cycle, 0x3=4Cycle 
 */
#define rTacc1                          (0x1:SHL:4)     /*  0x0=Disable, 0x1=2Cycle */
/*  0x2=3Cycle, 0x3=4Cycle
 *  0x4=5Cycle, 0x5=6Cycle
 *  0x6=7Cycle, 0x7=Reserved
 */
#define rROMCON1                        ROMEndPtr1+ROMBasePtr1+rTacc1+rTpa1+PMC1
/* -------------------------------------------------------------
 */

/* -> ROMCON2 : ROM Bank2 Control register */
/* -------------------------------------------------------------
 */
#define ROMBasePtr2                     0x004:SHL:10    /* =0x0040000   */
#define ROMEndPtr2                      0x008:SHL:20    /* =0x0080000   */
#define PMC2                            0x0             /*  0x0=Normal ROM, 0x1=4Word Page  */
/*  0x2=8Word Page, 0x3=16Word Page
 */
#define rTpa2                           (0x0:SHL:2)     /*  0x0=5Cycle, 0x1=2Cycle */
/*  0x2=3Cycle, 0x3=4Cycle 
 */
#define rTacc2                          (0x1:SHL:4)     /*  0x0=Disable, 0x1=2Cycle */
/*  0x2=3Cycle, 0x3=4Cycle
 *  0x4=5Cycle, 0x5=6Cycle
 *  0x6=7Cycle, 0x7=Reserved
 */
#define rROMCON2                        ROMEndPtr2+ROMBasePtr2+rTacc2+rTpa2+PMC2
/* -------------------------------------------------------------
 */

/* -> ROMCON3 : ROM Bank3 Control register */
/* -------------------------------------------------------------
 */
#define ROMBasePtr3                     0x060:SHL:10    /* =0x0600000   */
#define ROMEndPtr3                      0x080:SHL:20    /* =0x0800000   */
#define PMC3                            0x0             /*  0x0=Normal ROM, 0x1=4Word Page  */
/*  0x2=8Word Page, 0x3=16Word Page
 */
#define rTpa3                           (0x0:SHL:2)     /*  0x0=5Cycle, 0x1=2Cycle */
/*  0x2=3Cycle, 0x3=4Cycle 
 */
#define rTacc3                          (0x2:SHL:4)     /*  0x0=Disable, 0x1=2Cycle */
/*  0x2=3Cycle, 0x3=4Cycle
 *  0x4=5Cycle, 0x5=6Cycle
 *  0x6=7Cycle, 0x7=Reserved
 */
#define rROMCON3                        ROMEndPtr3+ROMBasePtr3+rTacc3+rTpa3+PMC3
/* -------------------------------------------------------------
 */

/* -> ROMCON4 : ROM Bank4 Control register */
/* -------------------------------------------------------------
 */
#define ROMBasePtr4                     0x080:SHL:10    /* =0x0800000   */
#define ROMEndPtr4                      0x0A0:SHL:20    /* =0x0A00000   */
#define PMC4                            0x0             /*  0x0=Normal ROM, 0x1=4Word Page  */
/*  0x2=8Word Page, 0x3=16Word Page
 */
#define rTpa4                           (0x0:SHL:2)     /*  0x0=5Cycle, 0x1=2Cycle */
/*  0x2=3Cycle, 0x3=4Cycle 
 */
#define rTacc4                          (0x4:SHL:4)     /*  0x0=Disable, 0x1=2Cycle */
/*  0x2=3Cycle, 0x3=4Cycle
 *  0x4=5Cycle, 0x5=6Cycle
 *  0x6=7Cycle, 0x7=Reserved
 */
#define rROMCON4                        ROMEndPtr4+ROMBasePtr4+rTacc4+rTpa4+PMC4
/* -------------------------------------------------------------
 */

/* -> ROMCON5 : ROM Bank5 Control register */
/* -------------------------------------------------------------
 */
#define ROMBasePtr5                     0x0A0:SHL:10    /* =0x0A00000   */
#define ROMEndPtr5                      0x0C0:SHL:20    /* =0x0C00000   */
#define PMC5                            0x0             /*  0x0=Normal ROM, 0x1=4Word Page  */
/*  0x2=8Word Page, 0x3=16Word Page
 */
#define rTpa5                           (0x0:SHL:2)     /*  0x0=5Cycle, 0x1=2Cycle */
/*  0x2=3Cycle, 0x3=4Cycle 
 */
#define rTacc5                          (0x4:SHL:4)     /*  0x0=Disable, 0x1=2Cycle */
/*  0x2=3Cycle, 0x3=4Cycle
 *  0x4=5Cycle, 0x5=6Cycle
 *  0x6=7Cycle, 0x7=Reserved
 */
#define rROMCON5                        ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC5
/* -------------------------------------------------------------
 */

/* -> DRAMCON0 : RAM Bank0 control register */
#define rDRAMCON0                       0
#define rSDRAMCON0                      0
/* -------------------------------------------------------------
 */

/* -> DRAMCON1 : RAM Bank1 control register */
#define rDRAMCON1                       0
#define rSDRAMCON1                      0
/* -------------------------------------------------------------
 */

/* -> DRAMCON2 : RAM Bank2 control register */
#define rDRAMCON2                       0
#define rSDRAMCON2                      0
/* -------------------------------------------------------------
 */

/* -> DRAMCON3 : RAM Bank3 control register */
#define rDRAMCON3                       0
#define rSDRAMCON3                      0
/* -------------------------------------------------------------
 */

/* -> REFEXTCON : External I/O & Memory Refresh cycle Control Register */
/* -------------------------------------------------------------
 */
#define RefCycle                        16    /* Unit [us], 1k refresh 16ms */
/* RefCycle        EQU   8   ;Unit [us], 1k refresh 16ms
 */
#define CASSetupTime                    0     /* 0=1cycle, 1=2cycle */
#define CASHoldTime                     0     /* 0=1cycle, 1=2cycle, 2=3cycle, */
/* 3=4cycle, 4=5cycle,
 */
#define RefCycleValue                   ((2048+1-(RefCycle*fMCLK)):SHL:21)
#define Tcsr                            (CASSetupTime:SHL:20)    /*  1cycle */
#define Tcs                             (CASHoldTime:SHL:17)    
#define ExtIOBase                       0x18360       /*  Refresh enable, VSF=1 */
/* 
 */
#define rREFEXTCON                      RefCycleValue+Tcsr+Tcs+ExtIOBase
/* -------------------------------------------------------------
 * SRefCycle       EQU   16   ;Unit [us], 4k refresh 64ms
 */
#define SRefCycle                       8    /* Unit [us], 4k refresh 64ms */
#define ROWcycleTime                    3     /* 0=1cycle, 1=2cycle, 2=3cycle, */
/* 3=4cycle, 4=5cycle,
 */
#define SRefCycleValue                  ((2048+1-(SRefCycle*fMCLK)):SHL:21)
#define STrc                            (ROWcycleTime:SHL:17)    
#define rSREFEXTCON                     SRefCycleValue+STrc+ExtIOBase
/* -------------------------------------------------------------
 */


#endif

/* 	END */