except.s

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        TTL     Angel exception support                 > except.s
        ; ---------------------------------------------------------------------
        ;
        ; This file provides the default Angel exception vector handlers.
        ;
        ; $Revision: 1.4 $
        ;   $Author: asims $
        ;     $Date: 1999/12/03 10:18:12 $
        ;
        ; Copyright Advanced RISC Machines Limited, 1995, 1997, 1998.
        ; All Rights Reserved
        ;
        ; ---------------------------------------------------------------------

        KEEP

        GET     listopts.s           ; standard listing control
        GET     lolevel.s            ; automatically built manifest definitions
        GET     macros.s             ; standard assembler support
        GET     target.s             ; target specific manifests
        GET     taskmacs.s


        EXPORT  __VectorStart
        EXPORT  __SoftVectors

        IMPORT  angel_IRQInterruptHandler
        IMPORT  angel_FIQInterruptHandler
        IMPORT  Angel_ExitToUSR
        IMPORT  __rt_asm_fatalerror
        IMPORT  ContextLookuptable
        IMPORT  Angel_SerialiseTask
	IF DEBUG = 1
	    IMPORT  Log_logmsginfo
	    IMPORT  log_loginfo
            IMPORT  angel_SysCallCount
	    IMPORT  Angel_DebugLog
	ENDIF
        IMPORT  angel_SWIReturnToApp
        IMPORT  angel_CurrentTask
        IMPORT  angel_ComplexSWILock
        IMPORT  Angel_StackBase
        IMPORT  angel_SWIDeferredBlock
        IMPORT  Angel_AccessApplicationTask
        IMPORT  Angel_DeferredBlockCore
        IMPORT  angel_SelectNextTask

      IF MINIMAL_ANGEL = 1

        AREA    |C$$zidata|,DATA,READWRITE,NOINIT

        EXPORT  Angel_GlobalRegBlock

Angel_GlobalRegBlock
        %       Angel_RegBlockSize * RB_NumRegblocks

        
      ELSE

        IMPORT  Angel_GlobalRegBlock

      ENDIF
        

        ; Default ARM hardware exception vectors
        ;
        ; When building ROM at zero systems, the link should be modified
        ; to force this area to be first.

      IF      ROMonly

	IF :DEF: ADS_BUILD :LAND: ADS_BUILD = 1
	        AREA    |__Vectors|,CODE,READONLY
	ELSE
        	AREA    |__Vectors|,CODE,PIC,READONLY
	ENDIF

      ELSE
        ; Masquerade as ReadWrite Code so that this AREA gets placed first
        ; in the Read-Write segment by the linker, and has two underscores
        ; to help it get sorted first in case anyone has any real RW Code !

	IF :DEF: ADS_BUILD :LAND: ADS_BUILD = 1
	        AREA    |__Vectors|,CODE,READWRITE
	ELSE
        	AREA    |__Vectors|,CODE,PIC,READWRITE
	ENDIF

      ENDIF

      EXPORT  |__Vectors|

        ;
        ; After initialisation the following vectors *MUST* start at
        ; 0x00000000 (an ARM processor requirement).
        ;
        ; The following vectors load the address of the relevent
        ; exception handler from an address table.  This makes it
        ; possible for these handlers to be anywhere in the address space.
        ;
        ; To bootstrap the ARM, some form of ROM is present at
        ; 0x00000000 during reset.  Often the startup code performs
        ; some target specific magic to remap RAM to address
        ; zero. The ROM based Read/Write data and BSS must then be
        ; copied to the relevant RAM address during the Angel ROM
        ; initialisation.
        ;
__VectorStart                   ; Start of ARM processor vectors
        LDR     pc,ResetV       ; 00 - Reset
        LDR     pc,UndefV       ; 04 - Undefined instructions
        LDR     pc,SWIV         ; 08 - SWI instructions
        LDR     pc,PAbortV      ; 0C - Instruction fetch aborts
        LDR     pc,DAbortV      ; 10 - Data access aborts
        LDR     pc,UnusedV      ; 14 - Reserved (was address exception)
        LDR     pc,IRQV         ; 18 - IRQ interrupts
        LDR     pc,FIQV         ; 1C - FIQ interrupts
        ;
        ; NOTE: In a normal optimised ARM system the FIQ vector would
        ; not contain a branch to handler code, but would have an
        ; allocation immediately following address 0x1C, with the FIQ
        ; code being placed directly after the vector table. This
        ; avoids the pipe-line breaks associated with indirecting to a
        ; handler routine.

        ; However Angel is designed to be a simple system so we
        ; treat FIQ like all the other vectors, and this allows the
        ; actual handler addresses to be stored immediately after the
        ; ARM vectors. If optimal FIQ entry is required, then space
        ; could be allocated at this point to hold the direct FIQ
        ; code. The __SoftVectors table would then simply appear
        ; higher in the RAM allocation.
        ;
__SoftVectors
        ; Reset - an error unless ROM always at zero, or a branch
        ; to High ROM on reset has been requested explicitly (Cogent Board)

        IMPORT  __rom
ResetV  
    IF ROMonly
        DCD     __rom                ; 00 - Reset, not mapped at boot
    ELSE
      IF BRANCH_TO_HIGH_ROM_ON_RESET <> 0
        DCD     ROMBase              ; 00 - Reset, remap ROM during boot (e.g. PID)
      ELSE
        DCD     __rom                ; 00 - Reset, mapped at boot
      ENDIF
    ENDIF
        
UndefV  DCD     HandlerUndef         ; 04 - undef
SWIV    DCD     HandlerSWI           ; 08 - software interrupt
PAbortV DCD     HandlerPrefetchAbort ; 0C - prefectch abort
DAbortV DCD     HandlerDataAbort     ; 10 - data abort
UnusedV DCD     0                    ; 14 - will reset if called...
IRQV    DCD     angel_IRQInterruptHandler ; 18 - IRQ
FIQV    DCD     angel_FIQInterruptHandler ; 1C - FIQ

        
__VectorEnd             ; End of Angel code copied to zero


	IF :DEF: ADS_BUILD :LAND: ADS_BUILD = 1
	        AREA    |ExceptionInit|,CODE,READONLY
	ELSE
        	AREA    |ExceptionInit|,CODE,PIC,READONLY
	ENDIF

      IF :LNOT: ROMonly

        ; This is removed for FLASH at 0 systems where a 
        ; write to the flash may cause reprogramming - in the case of the
        ; ATMEL devices on the PID. If ROM is at 0 there is no need to
        ; initialise the vectors as they are hard coded.
        
        ; This function performs the exception system initialisation:
        
        EXPORT angel_ExceptionInit
angel_ExceptionInit
        ; in:   no arguments
        ; out:  no result
        ;
        ; Here we copy the vector table (__VectorStart to __VectorEnd)
        ; to address 0.
        ; This is clearly necessary if we have a RAM based system, and
        ; is clearly pointless if we have a ROM at 0 based system.

        LDR     a1,=__VectorStart       ; start of data
        MOV     a2,#0x00000000          ; destination address
        LDR     a3,=__VectorEnd         ; end of data
01      LDR     a4,[a1],#4              ; get word from data AREA
        STR     a4,[a2],#4              ; store to RAM at zero
        CMP     a1,a3                   ; check for end condition
        BLO     %BT01                   ; if (a2 < a3) we have more to transfer
        ;
        MOV     pc,lr

      ENDIF ;:LNOT: ROMonly
        
        ; ****************************************************************
        ;
        ; void CallSerialiseTask(angel_Regblock *, int reason)
        ;                               r0             r2
        ;
        ; -------------------------------------------
        ; 
        ; Internal 'function': Set up a call to SerialiseTask to run
        ; the Angel ThreadStopped callback. The regblock which contains
        ; the context of the stopped thread is in r0, and the reason it
        ; stopped in r2. 
        ; 
        ; 
        ; 
        ; 
        ; THIS FUNCTION DOES NOT RETURN TO THE CALLER.
        ; 
        ; -------------------------------------------
      IF MINIMAL_ANGEL = 0

        IMPORT angelOS_ThreadStopped
CallSerialiseTask
        ; Now prepare to call Angel_SerialiseTask
        ; r0 and r2 are set up by caller
        ; r0 = register block to save to
        ; r2 = Stopped reason code to pass to debugger
        ;
        ; MRS     r1, CPSR
        ; EnableAngelInts r1, r1      ; enable angel interrupts or we can't do anything.
        ; MSR     CPSR_c, r1

        ; SerialiseTask expects:
        ; r0 = called_by_yield
        ; r1 = function to call (angelOS_ThreadStopped)
        ; r2 = type (already set up)
        ; r3 = empty_stack
        ; [sp] = save regblock
        
        LDR     r1, =angelOS_ThreadStopped
        MOV     r3, sp                  ; this MOV must be before the STMFD, below!
        STMFD   sp!, {r0}
        MOV     r0, #0
        B       Angel_SerialiseTask     ; Not coming back
        
        ; and angelOS_ThreadStopped will execute when SerialiseTask
        ; allows it to

      ENDIF

        
        ; *****************************************************************

        ; Exception handlers

	IF :DEF: ADS_BUILD :LAND: ADS_BUILD = 1
	        AREA    |DefaultVectorHandlers|,CODE,READONLY
	ELSE
        	AREA    |DefaultVectorHandlers|,CODE,PIC,READONLY
	ENDIF

        ; This is the ARM exception interface to the Angel debug world.
        ;
        ; This code provides the default ARM vector handlers for the
        ; processor exceptions. If the target application (or the
        ; more likely an O/S) does provide vector handlers,
        ; then they should be coded to provide the VectorCatch
        ; checking code performed below, to ensure that a debug agent
        ; can stop on system events. However, this is very system
        ; specific.
        ;
        ; By default the Angel debug world makes use of the
        ; Undefined Instruction exception, SWI's and eother IRQ's or
        ; FIQ's depending on which the board uses.  All of the
        ; other exceptions are unused by Angel, and the default action
        ; is purely to raise a debug event.
        ;
        ; The model used by the serialisation module is discussed
        ; in detail elsewhere.  This module follows the rules and
        ; guidelines laid out by the serialiser.

        ; in: UND mode; IRQs disabled; FIQs undefined
        ;     r13 = FD stack
        ;     r14 = address of undefined instruction + 4
        ;     All other registers must be preserved

        EXPORT HandlerUndef
        EXPORT HandlerDataAbort
        EXPORT HandlerPrefetchAbort
        IMPORT memory_is_being_accessed
        IMPORT memory_access_aborted
        
        
        ; ****************************************************************
        ;
        ; void HandlerPrefetchAbort()
        ;
        ; -------------------------------------------
        ; 
        ; 
        ; 
        ; -------------------------------------------
        
HandlerPrefetchAbort
        
      IF MINIMAL_ANGEL <> 0

        ;; we're not supposed to be handling this, so don't
        SUBS    pc, lr, #4
        
      ELSE
        
        EXCEPTENTRY_PART1 ABTmode, Angel_GlobalRegBlock + (RB_ABORT * Angel_RegBlockSize)
        LDR     r6, =ADP_Stopped_PrefetchAbort
        B       GenericAbort
        
      ENDIF
        
        ; ****************************************************************
        ;
        ; void HandlerDataAbort()
        ;
        ; -------------------------------------------
        ; 
        ; 
        ; 
        ; -------------------------------------------
        
HandlerDataAbort
        
      IF MINIMAL_ANGEL <> 0

        ;; we're not supposed to be handling this, so don't
        SUBS    pc, lr, #4
        
      ELSE
        
        EXCEPTENTRY_PART1 ABTmode, Angel_GlobalRegBlock + (RB_ABORT * Angel_RegBlockSize)
        LDR     r6, =ADP_Stopped_DataAbort
        
        ;; fall through to...
        ; B     GenericAbort
      ENDIF

        
      IF MINIMAL_ANGEL = 0
        
        IMPORT  angel_StartTask
GenericAbort

        ; Complete the exception entry sequence. This bit is not handler type
        ; specific. R6 contains the exception type code.
        
        EXCEPTENTRY_PART2
        
      IF DEBUG <> 0
        STMFD   sp!, {r0-r3,lr}
        MOV     r1, #0
        MOV     r2, #DL_AbortSave
        BL      Angel_DebugLog
        LDMFD   sp!, {r0-r3,lr}
      ENDIF

        ; The value of r14 has been decremented by 4, i.e. referring to the
        ; instruction after the aborted instruction.
        ; r0 points at (the start of) the regblock referred to in the
        ; entry macro.

        ; We have to check that the undefined instruction we hit
        ; was indeed the Angel Undefined instruction
        ;
        ; Clearly this uses different code for Thumb and ARM states
        ; but make the Thumb support code removable
        ;
        ; Note that r14_und has been adjusted to point to the undef
        ; (ARM or Thumb).
        LDR     r1, =memory_is_being_accessed
        LDR     r1, [r1]
        CMP     r1, #0
        BEQ     NotAngelOSAbort  ; Not due to debugger memory op aborting

        ; Now we know that it is either angelOS_MemRead or angelOS_MemWrite
        ; that has aborted. increment the abort count and return to the
        ; next instruction, continuing the loop. Eventually, the abort
        ; count will be used to detect which address first aborted.

        LDR     r1, =memory_access_aborted
        LDR     r2, [r1]
        ADD     r2, r2, #1
        STR     r2, [r1]
        
        ; r0 already has the regblock pointer -- just jump back...
        B       angel_StartTask