except.s

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;
; $Revision: 1.3 $
;   $Author: mechavar $
;     $Date: 2000/05/01 19:37:08 $
;
; Copyright (c) 2000 ARM, INC.
; All Rights Reserved
;
; ---------------------------------------------------------------------

	INCLUDE except_h.s
	INCLUDE except.a

	AREA	Exceptions, CODE

	IMPORT	uHALr_TrapSWI

; bslSWIHandler replaces the preexisting uHALr_TrapSWI as the SWI handler.
;  Derived from uHAL boot.s

	EXPORT	bslSWIHandler
bslSWIHandler
 ;  First check if this is an Angel SWI, which we let uHAL play with
	STMFD   sp!, {r10, r11, r12, lr} ; For compatablility with the AEB bsl
	
 IF :DEF: THUMB_AWARE   ; if interworking is required
	MRS     r10, spsr            ; Get spsr
	TST     r10, #PSR_T_bit      ; Occurred in Thumb state?
	LDRNEH  r10, [lr,#-2]        ; Yes: Load halfword and...
	BICNE   r10, r10, #0xFF00    ; ...extract comment field
	LDREQ   r10, [lr,#-4]        ; No: Load word and...
	BICEQ   r10, r10, #0xFF000000 ; ...extract comment field
   
        ; r10 now contains SWI number
        
	LDR	r11, =SWI_Angel     ; Is it an ARM State Angel SWI?
	CMP	r10, r11
	LDMEQFD	sp!, {r10, r11, r12, lr}
	BEQ	uHALr_TrapSWI

	LDR	r11, =SWI_Angel_Thumb
	CMP	r10, r11
	LDMEQFD	sp!, {r10, r11, r12, lr}
	BEQ	uHALr_TrapSWI

 ELSE
 ; ARM instructions only, no need to check for Thumb caller
	LDR	r10, [r14, #-4]		; Read SWI instruction
	BIC	r10, r10, #0xff000000	; extract the SWI number

	LDR	r11, =SWI_Angel
	CMP	r10, r11
	LDMEQFD	sp!, {r10, r11, r12, lr}
	BEQ	uHALr_TrapSWI

 ENDIF

 ; For testing purposes, just return
;	LDMFD	sp!, {r10, r11, r12, lr} ; restore register
;	MOV	r0, #0			; Pretend it was all okay
;	MOVS	pc, lr			; just ignore SWI

 ; Follow the code as taken more or less 'verbatim' from the AEB bsl to
 ;  support daemon SWIs

	IMPORT	   bsl_main

		IMPORT	OS_SWIHandler
		IMPORT	Write0
		IMPORT	NewLine
		IMPORT	WriteHex


                MOV     lr, #SWI_HANDLER
                B       ExceptionHandler

		IMPORT	ModuleSWI
	EXPORT DefSWIHandler
DefSWIHandler   STMDB   sp!, {r0-r9}
                MOV     r1, sp
                MOV     r0, r10
                CMP     r10, #0x100	; ECN: Under the old APCS I could just do
                BLCS    ModuleSWI	;      BLCS, BLCC
		CMP	r10, #0x100	; However, here we must redo the compare
                BLCC    OS_SWIHandler
                CMP     r0, #0
                LDMEQIA sp!, {r0-r12, pc}^
		MOV	lr, r0
		LDMIA	sp!, {r0-r12}
		SWP	lr, lr, [sp]
		LDMIA	sp!, {pc}
 
                EXPORT  EnterOS
EnterOS         MOV	pc, lr       ; Forgot to restore cpsr!
 
		EXPORT	HandleReportedError
		IMPORT	error_buff
HandleReportedError
		LDR	r0, =error_buff
		LDR	r0, [r0]
                EXPORT  ErrorHandler
ErrorHandler	STMDB	sp!, {r10, r11, r12, lr}
		MOV     r10, r0
                MOV     lr, #ERROR_HANDLER
                B       ExceptionHandler

                IMPORT  handlers
ExceptionHandler
                LDR     r12, =handlers
                LDR     r11, [r12, lr, LSL #3]!
; ECN: Sigh: The exception handler definition in Demon defines exactly what should
; be on the stack and leaves us no registers free to store the exception number.
; I guess we could assume that R11 will be preserved by the exception handler, but
; who knows. So we go though horrible contortions here.
		ADD	lr, pc, lr, LSL #3
                LDR     pc, [r12, #4]
RunAwayBTZ	MOV	r11, #BTZ_HANDLER
		B	DefExceptionHandler
RunAwayUndef	MOV	r11, #UNDEF_HANDLER
		B	DefExceptionHandler
RunAwaySWI	MOV	r11, #SWI_HANDLER
		B	DefExceptionHandler
RunAwayPrefetch	MOV	r11, #PREFETCH_HANDLER
		B	DefExceptionHandler
RunAwayAbort	MOV	r11, #ABORT_HANDLER
		B	DefExceptionHandler
RunAwayAddress	MOV	r11, #ADDRESS_HANDLER
		B	DefExceptionHandler
RunAwayIRQ	MOV	r11, #IRQ_HANDLER
		B	DefExceptionHandler
RunAwayFIQ	MOV	r11, #FIQ_HANDLER
		B	DefExceptionHandler
RunAwayError	MOV	r11, #ERROR_HANDLER

SWI_EnterOS		EQU	0x16

	EXPORT DefExceptionHandler
DefExceptionHandler
		STMDB	sp!, {r0-r9}
		MOV	r4, r11
		MOV	r5, sp
		MRS	r1, CPSR
		TST	r1, #User_Mode_Bits
		SWIEQ	SWI_EnterOS
		BICNE	r1, r1, #Mode_Bits
		ORRNE	r1, r1, #SVC_Mode
		MSRNE	CPSR_c, r1
	RESET_SVC_STACK
		BL	NewLine
		ADR	r0, ExceptionMsgs
		LDR	r0, [r0, r4, LSL #2]
		BL	Write0
		ADR	r0, %FT1
		BL	Write0
		LDR	r0, [r5, #13 * 4]
		MOV	r1, #8
		BL	WriteHex
		BL	NewLine
		B	bsl_main
1
		DCB	" at PC=", 0
		ALIGN

ExceptionMsgs	DCD	BTZ_Msg
		DCD	Undef_Msg
		DCD	SWI_Msg
		DCD	Prefetch_Msg
		DCD	Abort_Msg
		DCD	Address_Msg
		DCD	IRQ_Msg
		DCD	FIQ_Msg
		DCD	Error_Msg
BTZ_Msg		DCB	"Branch through zero", 0
Undef_Msg	DCB	"Undefined instruction", 0
SWI_Msg		DCB	"SWI", 0
Prefetch_Msg	DCB	"Prefetch", 0
Abort_Msg	DCB	"Abort", 0
Address_Msg	DCB	"Address exception", 0
IRQ_Msg		DCB	"IRQ", 0
FIQ_Msg		DCB	"FIQ", 0
Error_Msg	DCB	"Error", 0
		ALIGN

	EXPORT DefErrorHandler
DefErrorHandler
	RESET_SVC_STACK
		BL	NewLine
		ADD	r0, r10, #4
		BL	Write0
		BL	NewLine
		B	bsl_main

	EXPORT IRQHandler
IRQHandler      STMDB   sp!, {r10, r11, r12, lr}
                MOV     lr, #IRQ_HANDLER
                B       ExceptionHandler


	
	END