📄 spi.c
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}
}
else //one row data transmit end
{
SET_BIT(PORT_SPI,SS); //pull up the SS,end the transmit
SPI_once_end_flag = 0x01; //out of data write
CLR_BIT(SPCR,7); //disable SPI interrupt
}
}
}
else if((SPI_end_flag == 0x01) && (SPI_Rstatus_flag == 3)) //send protected code
{
SPI_pro_flag++;
if(SPI_pro_flag == 1)
{
SET_BIT(PORT_SPI,SS); //pull up the SS
CLR_BIT(PORT_SPI,SS); //pull down the SS
SPDR = WRSR;
}
else if(SPI_pro_flag == 2)
{
SPDR = ALL_PROTECTED; //eeprom all blocks program disable
}
else if(SPI_pro_flag == 3)
{
SET_BIT(PORT_SPI,SS); //pull up the SS
CLR_BIT(PORT_SPI,SS);
SPDR = WRDI; //disable all programming modes
}
else if(SPI_pro_flag == 4)
{
SET_BIT(PORT_SPI,SS); //pull up the SS
SPI_rx_flag = 0x01;
}
}
}
//*************test if the eeprom is write or not***********************************
else
{
SPI_rx_counter++;
if(SPI_rx_counter == 1)
{
SPDR = uart_ping_data[2]; //the address hihg byte
}
else if(SPI_rx_counter == 2)
{
SPDR = uart_ping_data[3]; //the address low byte
}
else if(SPI_rx_counter == 3) //the second time enter the interrutp
{
SPDR = 0xFF; //invalid data
}
else if(SPI_rx_counter <= 35)
{
SPDR = 0xFF;
SPI_rx_buffer[SPI_rx_counter - 4] = SPDR;
}
else if(SPI_rx_counter == 37)
{
SPDR = 0xFF;
}
else if(SPI_rx_counter == 38)
{
//SPDR = 0xFF;
SPI_rx_buffer[32] = SPDR;
}
else
{
SET_BIT(PORTD,7);
SET_BIT(PORTD,6);
SET_BIT(PORT_SPI,SS);
}
}
//***********************************************************************
}
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//transmit array data byte,
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
void put_spi_char()
{
uchar i;
uchar temp_dataf;//temp_datas;
if((SPI_end_flag == 0x00) && (SPI_once_end_flag == 0x01))//transmit not end one row datas in tx buffer are transmitted
{
CLR_BIT(SPCR,7); //disable SPI interrupt
SPI_once_end_flag = 0x00; //clear the flag,for interrupt transmit
if(SPI_start_flag == 0x00) //at the beginning of transmit
{
SPI_start_flag = 0x01; //set the flag
P_SPI_tx = dspcode; //piont at the first data,
}
else
{
temp_dataf = (*P_SPI_tx) + 3;
P_SPI_tx += temp_dataf; //set the piont
}
if(SPI_all_end_flag == 0x01)
{
//__disable_interrupt();
//eep_program_disable(); //all blocks protected enable
//__enable_interrupt();
SPI_end_flag = 0x01; //set the data are all transmit flag
SPI_op_code = 0x00; //ready for send write enable op_code
//SET_BIT(PORT_SPI,SS); //pull up the SS,end the transmit
SPI_Rstatus_flag = 0x00; //clear the read status flag ***
//SPI_rx_flag = 0x01; //read eeprom enable
}
else
{
if((*P_SPI_tx) != 0x00) //not at the end of transmition
{
for(i = 0; i < (*P_SPI_tx); i++) //data number,first data
SPI_tx_buffer[i] = *(P_SPI_tx + i + 3); //write the buffer
SPI_tx_counter = 0x00; //clear the number counter
SPI_op_code = 0x00; //start another array transmit
SPI_Rstatus_flag = 0x00; //clear the read status flag
SPI_tx_addl = *(P_SPI_tx + 2);
SPI_tx_addh = *(P_SPI_tx + 1);
//temp_dataf = SPI_tx_addl;
//temp_datas = 3 * SPI_tx_row;
//SPI_tx_addl += temp_datas; //address +3 +14
//if(SPI_tx_addl < temp_dataf) //adjust the address,overflow
//{
// SPI_tx_addh += 1; //high address +1
//}
//SPI_tx_row++; //prepare for next row transmit
}
else //transmit end
{
SPI_all_end_flag = 0x01; //set all data transfer end flag
SPI_tx_buffer[0] = 0x00;
SPI_tx_buffer[1] = 0x00; //write end flag data
temp_dataf = SPI_tx_addl; //ajust the address
SPI_tx_addl += SPI_tx_counter;
if(SPI_tx_addl < temp_dataf)
{
SPI_tx_addh += 1; //high address +1
}
P_SPI_tx -= (SPI_tx_counter + 3); //ajust the value of (*P_SPI_tx)
SPI_tx_counter = 0x00; //clear the number counter
SPI_op_code = 0x00; //start another array transmit
//SPI_tx_row = 0x00; //prepare for next row transmit
SPI_Rstatus_flag = 0x00; //clear the read status flag
}
}
SET_BIT(SPCR,7); //Enable SPI interrupt
}
}
//*******************************************
void get_spi_char()
{
;
}
//************************************************************************
//under we will write protected enable op_code, use looking for mode
//*************************************************************************
void eep_program_enable()
{
uchar temp_data;
SET_BIT(PORT_SPI,SS); //pull up SS
temp_data = SPSR;
temp_data = SPDR; //clear the SPIF flag
CLR_BIT(PORT_SPI,SS); //pull down the SS
SPDR = WREN; //set write enable latch
while((SPSR & 0x80) == 0x00); //wait for transfer complete
SET_BIT(PORT_SPI,SS); //pull up the SS
temp_data = SPSR;
temp_data = SPDR; //clear the SPIF flag
CLR_BIT(PORT_SPI,SS); //pull down the SS
SPDR = WRSR; //send the write Status register op_code
while((SPSR & 0x80) == 0x00); //wait for transfer complete
temp_data = SPSR;
temp_data = SPDR; //clear the SPIF flag
SPDR = ALL_NOT_PRO; //send not protected blocks op_code
while((SPSR & 0x80) == 0x00); //wait for transfer complete
SET_BIT(PORT_SPI,SS); //pull up the SS
temp_data = SPSR;
temp_data = SPDR; //clear the SPIF flag
}
void eep_program_disable()
{
//uchar i;
uchar temp_data; //read the SPSR\SPDR register for clear the SPIF flag
SET_BIT(PORT_SPI,SS); //pull up SS
temp_data = SPSR;
temp_data = SPDR; //clear the SPIF flag
CLR_BIT(PORT_SPI,SS); //pull down the SS
SPDR = WREN; //set write enable latch
while((SPSR & 0x80) == 0x00); //wait for transfer complete
SET_BIT(PORT_SPI,SS); //pull up the SS
temp_data = SPSR;
temp_data = SPDR; //clear the SPIF flag
CLR_BIT(PORT_SPI,SS); //pull down the SS
SPDR = WRSR; //send the write Status register op_code
while((SPSR & 0x80) == 0x00); //wait for transfer complete
temp_data = SPSR;
temp_data = SPDR; //clear the SPIF flag
SPDR = ALL_PROTECTED; //send protected all blocks op_code
while((SPSR & 0x80) == 0x00);
SET_BIT(PORT_SPI,SS); //pull up the SS
temp_data = SPSR;
temp_data = SPDR; //clear the SPIF flag
CLR_BIT(PORT_SPI,SS);
SPDR = WRDI; //send write disable op_code
while((SPSR & 0x80) == 0x00); //wait for transfer complete
SET_BIT(PORT_SPI,SS); //pull up the SS
temp_data = SPSR;
temp_data = SPDR; //clear the SPIF flag
}
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