cicmodule.v

一个3阶的CIC内插滤波器

//internalclk >= 8*outputclk

module cicmodule
(inputclk, internalclk, outputclk, preset, datainput, dataoutput);
parameter DataWidth=18;

parameter OutputDiv=4;  //OutputDiv=(order-1)*ln(outputclk/inputclk)/ln(2)

input inputclk;
input internalclk;
input outputclk;
input preset;
input signed [(DataWidth-1):0] datainput;
output signed [(DataWidth-1):0] dataoutput;

//registers
reg inputclkperiod;
reg [2:0] statecount;
reg signed [(DataWidth-1):0] inputreg;  

//--stage 1 (comb) signals,gain=2 -> + 1 bit
reg signed [DataWidth:0] int0;

//--stage 2 (comb) signals,gain=2 -> + 1 bit
reg signed [DataWidth+1:0] int1;

//--stage 3 (comb) signals,gain=2 -> + 1 bit
reg signed [DataWidth+2:0] int2;
reg signed [DataWidth+2:0] tempreg0;
reg signed [DataWidth+2:0] tempreg1;

//--stage 4 (integrator) signals,gain=2 -> + 1 bit
reg signed [DataWidth+4:0] int3;

//--stage 5 (integrator) signals,gain=0.5 -> - 1 bit
reg signed [DataWidth+5:0] int4;

//--stage 6 (integrator) signals,gain=4 -> + 2 bit
reg signed [DataWidth+7:0] int5;

reg signed [DataWidth+7:0] addInputA;
reg signed [DataWidth+7:0] addInputB;
reg signed [DataWidth+7:0] addInputBsig;
reg addsubSelect;
wire signed [DataWidth+7:0] addOutput;

//Add/sun
always @ (addInputB or addsubSelect)
begin 
if (addsubSelect)
addInputBsig=-addInputB;
else
addInputBsig=addInputB;
end

//Add
assign addOutput=addInputA+addInputBsig;

//Output assign
assign dataoutput=int5>>>OutputDiv;

//Clk operations
always @ (posedge inputclk or posedge outputclk or posedge preset)
begin
if (preset==1)
inputclkperiod=1;
else if(inputclk==1)
inputclkperiod=1;
else 
inputclkperiod=0;
end

always @ (posedge inputclk or posedge preset)
begin
if (preset==1'b1)
inputreg=0;
else
inputreg =datainput;
end

always @ (posedge internalclk or posedge inputclk or posedge preset)
begin
if(preset==1)
statecount=0;
else if (inputclk==1)
statecount=0;
else
statecount=statecount+1;
end

always @ (negedge internalclk or posedge preset)
begin
if(preset==1) begin 
tempreg0=0;
tempreg1=0;
int0=0;
int1=0;
int2=0;
int3=0;
int4=0;
int5=0;
end
else begin
case (statecount)
3'd0: begin
if (inputclkperiod==1) begin
tempreg0=addOutput;
int0=inputreg;
end
end
3'd1: begin
if (inputclkperiod==1) begin
tempreg1=addOutput;
int1=inputreg;
end
end
3'd2: begin
if (inputclkperiod==1) begin
int2=inputreg1;
tempreg0=addOutput;
end
end
3'd3: begin
int3=addOutput;
end
3'd4: beign
int4=addOutput;
end
3'd5: begin
int5=addOutput;
end
endcase
end
end

//Combinatorial logic
always @ (statecount, inputreg,int0, int1, int2, int3, int4, int5,
        tempreg0,tempreg1, inputclkperiod)
begin
case (statecount)
3'd0: begin
addInputA=inputreg;
addInputB=int0;
addsubSelect=1;
end
3'd1: begin
addInputA=tempreg0;
addInputB=int1;
addsubSelect=1;
end
3'd2: begin
addInputA=tempreg1;
addInputB=int2;
addsubSelect=1;
end
3'd3: begin
addInputA=int3;
addInputB=(inputclkperiod == 1'b1) ? tempreg0 : 0;
//Upsampling
addsubSelect=0;
end
3'd4: begin
addInputA=int4;
addInputB=int3;
addsubSelect=0;
end
3'd5: begin
addInputA=int5;
addInputB=int4;
addsubSelect=0;
end
endcase
end

endmodule