📄 peripheral.c
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}
/*10. no need to do anything*/
}
/*functions for the dmax*/
void init_dmax_mcasp0()
{
//dMAX event high priority
*(int *)(DMAX_CONTREG_BASE_ADD + DMAX_DEHPR)
= (0x1 << 7) //EHP7 set as a high-priority event
+ (0x1 << 6); //EHP6 set as a high-priority event
//dMAX event low priority
*(int *)(DMAX_CONTREG_BASE_ADD + DMAX_DELPR)
= 0x0000; //no effect
//dMAX event polarity
*(int *)(DMAX_CONTREG_BASE_ADD + DMAX_DEPR)
= (0x1 << 7) //event flag is set on rising edge
+ (0x1 << 6); //event flag is set on rising edge
//event entry(event #7 entry) -SIN
*(int *)(DMAX_HiMAX_EVENT_ENTRYADD + 7 * 4)
= 0x03 //ETYPE set to "00011"
+ (0x28 << 8) //PTE = 0101000, pointer to transfer entry #0
+ (0x52 << 16) //ESIZE = 10,32-bit element
//CC = 00,COUNT2(ACTIVE) is 16bits
//RLOAD = 1
//TCINT = 1
//ATCINT = 0
+ (0x83 << 24); //TCC = 0011,TCC3
//SYNC = 0
//QTSL = 10
//event entry(event #6 entry) -SOUT
*(int *)(DMAX_HiMAX_EVENT_ENTRYADD + 6 * 4)
= 0x03 //ETYPE set to "00011"
+ (0x33 << 8) //PTE = 0110011,pointer to transfer entry #1
+ (0x52 << 16) //ESIZE = 10,32-bit element
//CC = 00,COUNT2(ACTIVE) is 16 bits
//RLOAD = 1,reload
//TCINT = 1,?
//ATCINT = 0,?
+ (0x82 << 24); //TCC = 0010,TCC2
//SYNC = 0
//QTSL = 10
//********************* entry #0 *****************************
//transfer entry #0
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x00)
= 0x54000000; //SRC is DMA port at 0x54000000
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x04)
= 0x10001000; //DST is internal RAM
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x08)
= 0x01 //COUNT0A = 0x01
+ (0x02 << 8) //COUNT1A = 0x02
+ (0x80 << 16) //COUNT2A = 0x80
+ (0x00 << 24); //PP = 0
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x0C)
= 0x0000 //SINDX0 = 0x0000
+ (0x0000 << 16); //DINDX0 = 0x0000
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x10)
= 0x0000 //SINDX1 = 0x0000
+ (0x0080 << 16); //DINDX1 = 0x0080
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x14)
= 0x0000 //SINDX2 = 0x0000
+ (0xFF01 << 16); //DINDX2 = 0xFF01 (-127)
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x18)
= 0x01 //COUNT0R = 0x01
+ (0x02 << 8) //COUNT1R = 0x02
+ (0x80 << 16) //COUNT2R = 0x80
+ (0x00 << 24); //
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x1C)
= 0x54000000; //SRC0 is DMA port at 0x54000000
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x20)
= 0x10001000; //DST0 is internal RAM
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x24)
= 0x54000000; //SRC1 is DMA port at 0x54000000
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x28)
= 0x10001400; //DST1 is internal RAM
//******************* entry #1 ***************************
//transfer entry #1
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x2C + 0x00)
= 0x10001400; //SRC is DMA port at 0x54000000
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x2C + 0x04)
= 0x54000004; //DST is internal RAM
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x2C + 0x08)
= 0x01 //COUNT0A = 0x01
+ (0x02 << 8) //COUNT1A = 0x02
+ (0x80 << 16) //COUNT2A = 0x80
+ (0x00 << 24); //PP = 0
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x2C + 0x0C)
= 0x0000 //SINDX0 = 0x0000
+ (0x0000 << 16); //DINDX0 = 0x0000
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x2C + 0x10)
= 0x0080 //SINDX1 = 0x0080
+ (0x0000 << 16); //DINDX1 = 0x0000
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x2C + 0x14)
= 0xFF01 //SINDX2 = 0x0000
+ (0x0000 << 16); //DINDX2 = 0xFF01 (-127)
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x2C + 0x18)
= 0x01 //COUNT0R = 0x01
+ (0x02 << 8) //COUNT1R = 0x02
+ (0x80 << 16) //COUNT2R = 0x80
+ (0x00 << 24); //
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x2C + 0x1C)
= 0x10001400; //SRC0 is internal RAM
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x2C + 0x20)
= 0x54000004; //DST0 is DMA port at 0x54000004
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x2C + 0x24)
= 0x10001000; //SRC1 is internal RAM
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + 0x2C + 0x28)
= 0x54000004; //DST1 is DMA port at 0x54000004
*(int *)(DMAX_HiMAX_TRANSFER_ENTRYADD + DMAX_DEER)
= (0x01 << 6) //event 6 is enable
+ (0x01 << 7) //event 7 is enable
;
}
//*PLL initialize***/
void init_pll()
{
unsigned char i;
short j;
int itmp;
while(1)
{
itmp = *(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLCSR);
if(itmp & 0x00000040) //wait for oscillator to be stable
break;
}
itmp = *(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLCSR);
itmp &= 0xFFFFFFFE;
*(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLCSR)
= itmp; //PLLEN = 0
asm(" nop ");
asm(" nop ");
asm(" nop ");
asm(" nop ");
itmp &= 0xFFFFFFEF;
*(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLCSR)
= itmp; //PLLPWRDN = 0,wake up the PLL
itmp |= 0x00000008;
*(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLCSR)
= itmp; //PLLRST = 1
*(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLDIV0)
= 0x00008000; //divider0 is enable , divide frequency by 1
*(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLM)
= 0x0000000A; //*10 multiplier rate(200MHz)
while(1)
{
itmp = *(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLSTAT);
if(!(itmp & 0x00000001)) //check that the GOSTAT bit is cleared(no GO on progress)
break;
}
*(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLDIV1)
= 0x00008009; //divider1 is enable , divide frequency by 1
//used by the CPU
*(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLDIV2)
= 0x00008009; //divider2 is enable , divide frequency by 2
//used by the dMAX
*(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLDIV3)
= 0x00008001; //divider3 is enable , divide frequency by 2 (100MHz)
//used by the EMIF
*(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_ALNCTL)
= 0x00000007; //ALN1-3 bits all set to 1
//aligned SYSCLK1-3
*(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLCMD)
= 0x00000001; //GOSET bit set to 1
//change the divide values and align SYSCLK1-3
while(1)
{
itmp = *(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLSTAT);
if(!(itmp & 0x00000001)) //make sure GOSTAT bit goes back to o(GO has completed)
break;
}
//here wait for PLL reset
i = 10;
while(i--)
{
//itmp = *(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLCSR);
//if(!(itmp & 0x00000001)) //wait for PLL to properly reset(MIN 125 ns)
// break;
asm(" nop "); //wait for PLL to properly reset(MIN 125 ns)
}
itmp = *(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLCSR);
itmp &= 0xFFFFFFF7;
*(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLCSR)
= itmp; //PLLRST = 0
for(j = 0;j < 2000;j++)
{
i = 10;
while(i--)
{
asm(" nop "); //wait for PLL to lock(187.5us MIN)
}
}
*(int *)(DEVICE_CONTREG_CFGBRIDGE)
= 0x00000001; //reset the CFGBRIDGE
itmp = *(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLCSR);
itmp |= 0x00000001;
*(int *)(PLL_CONTREG_BASE_ADD + PLL_CONTREG_PLLCSR)
= itmp; //PLLEN = 1,enable PLL mode
}
//************* functions for the emif ****************************/
//FOR SDRAM:
//EM_CLK = 100MHz
//
void init_emif()
{
int itmp;
//configure SDRAM
itmp = *(int *)(EMIF_CONTREG_BASE_ADD + EMIF_CONTREG_SDCR);
itmp |= 0x10000000;
*(int *)(EMIF_CONTREG_BASE_ADD + EMIF_CONTREG_SDCR)
= itmp; //set SR bit of SDCR
//init_pll(); //programmed SYSCLK3 of PLL;
itmp &= 0x7FFFFFFF;
*(int *)(EMIF_CONTREG_BASE_ADD + EMIF_CONTREG_SDCR)
= itmp; //clear SR bit of SDCR
*(int *)(EMIF_CONTREG_BASE_ADD + EMIF_CONTREG_SDTIMR)
= 0x61114610; //SDTIMR
*(int *)(EMIF_CONTREG_BASE_ADD + EMIF_CONTREG_SDSRETR)
= 0x00000006; //SDSRETR
*(int *)(EMIF_CONTREG_BASE_ADD + EMIF_CONTREG_SDRCR)
= 0x00000061; //SDRCR
*(int *)(EMIF_CONTREG_BASE_ADD + EMIF_CONTREG_SDCR)
= 0x00004720; //SDCR
//configure the flash
*(int *)(EMIF_CONTREG_BASE_ADD + EMIF_CONTREG_A1CR) //A1CR
= 0x24BD
+ (0x22 << 16)
+ (0x94 << 24);
}
/*functions for the spi*/
void init_spi0()
{
}
/*functions for the mcasp0*/
/********************************************************************
end of file peripheral.c
********************************************************************/
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