peripheral.c

实现了TI的C672x写列DSP的dMAX服务于MCASP的配置,

/*****************************************************************************
created by ckq;2007-3-16
file name : peripheral.c
*****************************************************************************/

#include "functions.h"
#include "peripheral.H"
void init_interrupt()
{
	/*Global Int Diable*/
	CSR = CSR & ~0x1;
	/*Enable the NMI in the IER,for this bit must be initialized first*/
	IER = IER | (0x1 << 1);//
	/*Enable the bit in the IER*/
	IER = IER | (0x1 << 7);//n means the interrupt's number

	//IER |= 0xff00;

	/*Global Int Enable*/
	CSR = CSR | 0x1;
}
/*functions for the mcasp0*/
void init_mcasp0()
{
	int itmp;
	/*initial the Mcasp,
	  1st must reset Mcasp by set the GBLCTL to 0*/
	*(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL)
	= 0x00000000
					;
	/*2nd set the registers*/
	/*a. free run mode*/
	*(int *)(MCASP0_BASE_ADD + MCASP_PWRDEMU)
	= 0x00000001
					;
	/*b. receive function*/
	/*configure the rmsk of the receive*/
	*(int *)(MCASP0_BASE_ADD + MCASP_RMASK)
	= 0xFFFFFFFF
					;
	/*configure the receive format*/
	*(int *)(MCASP0_BASE_ADD + MCASP_RFMT)
	= (0x01 << 16)	//1-bit delay
	+ (0x01 << 15)	//MSB first
	+ (0x00 << 13)	//not used,because no mask bit
	+ (0x00 << 8)	//not used
	+ (0x0F << 4)	//slot size 32
	+ (0x00 << 3)	//read data from the dMAX port		???
	+ (0x00 << 0)	//not used,no rotation
					;
	/*configure the receive frame sync signal*/
	*(int *)(MCASP0_BASE_ADD + MCASP_AFSRCTL)
	= (0x02 << 7)	//I2S mode
	+ (0x01 << 4)	//signal word frame					???
	+ (0x00 << 0)	//externally-generated frame signal
	+ (0x01 << 0)	//falling edge start
					;
	/*configure the receive clk*/
	*(int *)(MCASP0_BASE_ADD + MCASP_ACLKRCTL)
	= (0x01 << 7)	//rising edge get data
	+ (0x00 << 0)	//clk from external
	+ (0x0)	 		//not used,divide-by-1
					;
	/*configure the receive hclk*/
	*(int *)(MCASP0_BASE_ADD + MCASP_AHCLKRCTL)
	= 0x00000000	//not use this signal
					;//
	/*configure the receive rtdm*/
	*(int *)(MCASP0_BASE_ADD + MCASP_RTDM)
	= 0x00000003	//receive slot 0 and 1 is active, ???
					;//
	/*configure the receive interrupt*/
	*(int *)(MCASP0_BASE_ADD + MCASP_RINTCTL)
	= 0x00000000	//(0x1<<5)	//must config it at step 5	???
					;//
	/*configure the receive RCLKCHK*/
	*(int *)(MCASP0_BASE_ADD + MCASP_RCLKCHK)
	= 0x00000000	//not used								???
					;//
	/*use the external clk must run the external clk first,for the proper GBLCTL*/
	/*c. transmit function*/
	/*configure the transmit mask*/
	*(int *)(MCASP0_BASE_ADD + MCASP_XMASK)
	= 0xFFFFFFFF	//use all 32 bit
					;//
	/*configure the transmit format*/
	*(int *)(MCASP0_BASE_ADD + MCASP_XFMT)
	= (0x01 << 16)	//1-bit delay
	+ (0x01 << 15)	//MSB first
	+ (0x00 << 13)	//not used
	+ (0x00 << 8)	//not used
	+ (0x0F << 4)	//slot size 32
	+ (0x00 << 3)	//writes data from the dMAX port
	+ (0x00 << 0)	//not used	
					;
	/*configure the transmit frame sync signal*/
	*(int *)(MCASP0_BASE_ADD + MCASP_AFSXCTL)
	= (0x02 << 7)	//I2S mode
	+ (0x01 << 4)	//signal word frame
	+ (0x00 << 0)	//external frame signal
	+ (0x01 << 0)	//falling edge start
					;
	/*configure the transmit clk*/
	*(int *)(MCASP0_BASE_ADD + MCASP_ACLKXCTL)
	= ( 0x01 << 7)	//rising edge get data
	+ ( 0x00 << 0)	//transmit and receive synchronous,clk from external
	+ ( 0x00 )	 	//not used,divide-by-1
					;
	/*configure the transmit hclk*/
	*(int *)(MCASP0_BASE_ADD + MCASP_AHCLKXCTL)
	= 0x00000000	//not use this signal
					;//
	/*configure the transmit rtdm*/
	*(int *)(MCASP0_BASE_ADD + MCASP_XTDM)
	= 0x00000003	//transmit slot 0 and slot 1 is active,why reading has only one slot active ???
					;//
	/*configure the transmit interrupt*/
	*(int *)(MCASP0_BASE_ADD + MCASP_XINTCTL)
	= 0x00000000	//(0x1<<5)			 //must config it at step 5
					;//
		/*configure the transmit xclkchk*/
	*(int *)(MCASP0_BASE_ADD + MCASP_XCLKCHK)
	= 0x00000000	//not used
					;//
	/*use the external clk must run the external clk first,for the proper GBLCTL*/
	/*d. serializer*/
	/*for the reset value is 0,no need to initialize the other pins*/
	/*axr6 sdout*/
	*(int *)(MCASP0_BASE_ADD + MCASP_SRCTL6)
	= (0x03 << 2)	//when inactive,keep high this pin
	+ (0x01 << 0)	//used as output pin,transmiter
					;//
	/*axr7 sdin*/
	*(int *)(MCASP0_BASE_ADD + MCASP_SRCTL7)
	= (0x03 << 2)	//when inactive,keep high this pin
	+ (0x02 << 0)	//used as input pin,receiver
					;//
	/*e. global register configuration*/
	/*Global PFUNC*/
	*(int *)(MCASP0_BASE_ADD + MCASP_PDIR)
	= 0x00000000	//default as input
					;

	*(int *)(MCASP0_BASE_ADD + MCASP_PFUNC)
	= (0x25 << 25)	//AMUTE\AHCLKX\AHCLKR pins as GPIO function
	+ (0x0F << 9)	//set AXR9-12 pins as GPIO function
	+ (0x3F << 0)	//set AXR0-5 pins as GPIO function
					;//others are Mcasp function
	/*Pin dir*/
	*(int *)(MCASP0_BASE_ADD + MCASP_PDIR)
	= (0x25 << 25)	//AMUTE\AHCLKX\AHCLKR pins as output
	+ (0x0F << 9)	//set AXR9-12 pins as output 
	+ (0x7F << 0)	//set AXR0-5 pins as output,AXR6 is SDOUT
					;//others are input 
	/*Pin dir*/
	*(int *)(MCASP0_BASE_ADD + MCASP_DITCTL)
	= 0x00000000	 //DIT mode is disable
					;//
	/*Pin DLBCTL*/
	*(int *)(MCASP0_BASE_ADD + MCASP_DLBCTL)
	= 0x00000000	//Loopback mode is disable
					;//
	/*Pin MCASP_AMUTE*/
	*(int *)(MCASP0_BASE_ADD + MCASP_AMUTE)
	= 0x00000000	 //AMUTE pin is disable
					;//
	/*f. not use DIT,so no need to config these registers*/
	/*3. config hclk;not used*/
	/*start the respective high-frequency serial clocks(setp 3)*/
	*(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL)
	= 0x00000202	//take out of reset high-frequency serial clock divider(s)
					;//
	while(1)
	{
		itmp = *(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL);
		if(itmp == 0x0202)
			break;
	}
	/*4. config clk;for external clk used,skipped*/
	
	/*********************************************************/
	/*5. dma	*/
	/*a			*/
	init_dmax_mcasp0();				//initialize the dMAX

	*(int *)(MCASP0_BASE_ADD + MCASP_REVTCTL)
	= 0x00000000	//receive data DMA requests is enable				
					;
	*(int *)(MCASP0_BASE_ADD + MCASP_XEVTCTL)
	= 0x00000000	//transmit data DMA requests is enable
					;
	/*********************************************************/
	/*configure the receive interrupt*/
	*(int *)(MCASP0_BASE_ADD + MCASP_RINTCTL)
	= (0x01 << 5)	//must config it at step 5
					;//
	/*configure the transmit interrupt*/
	*(int *)(MCASP0_BASE_ADD + MCASP_XINTCTL)
	= (0x01 << 5)	//must config it at step 5
					;//
	/*6. activate serializers*/
	/*a. clear status*/
	*(int *)(MCASP0_BASE_ADD + MCASP_RSTAT)
	= 0x0000FFFF	//clear the receiver status register
					;//
	//set these  and ACLKR must on
	itmp = *(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL);
	itmp |= 0x00000004;
	*(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL)
	= itmp			//start RSR
					;
	*(int *)(MCASP0_BASE_ADD + MCASP_XSTAT)
	= 0x0000FFFF	//clear the transmitter status register
					;//
	/*b. start serializers by setting the related bits in GBLCTL*/
	//*(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL)
	//= (0x01 << 10)	//start XSR
	//+ (0x01 << 2) 	//start RSR
						//;
	//set these two bits,the ACLKX and ACLKR must on
	itmp = *(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL);
	itmp |= 0x00000400;
	*(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL)
	= itmp			//start XSR
					;
	/*c. read back the set to ensure*/
	while(1)
	{
		itmp = *(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL);
		if((itmp & (0x01 << 10)) && (itmp & (0x01 << 2)))	
			break;
	}
	/*7. waite for the transmit ready*/
	//*a

	itmp = *(int *)(MCASP0_BASE_ADD + MCASP_XSTAT);
	itmp |= 0x00000020;
	*(int *)(MCASP0_BASE_ADD + MCASP_XSTAT)
	= itmp			//
					;	

	while(1)
	{
		itmp = *(int *)(MCASP0_BASE_ADD + MCASP_XSTAT);
		itmp |= 0x00000020;
		*(int *)(MCASP0_BASE_ADD + MCASP_XSTAT)
		= itmp		//
					;
		itmp = *(int *)(MCASP0_BASE_ADD + MCASP_XSTAT);
		if(!(itmp & 0x0020))	
			break;
	}
	/*8. start the state machine*/
	//release state machine
	itmp = *(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL);
	itmp = itmp
	+ (0x01 << 11)	//XSMRST release
	+ (0x01 << 3)	//RSMRST release
					;
	*(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL)
	= itmp			//	
	       			;
	//test state machine
	while(1)
	{
		itmp = *(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL);
		if(itmp & ((0x1 << 11) + (0x1 << 3))) 
			break;
	}
	/*9. start the frame logic*/
	//release frame logic
	itmp = *(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL);
	itmp = itmp
	+ (0x01 << 12)	//XFRST release
	+ (0x01 << 4)	//RFRST release
					;
	*(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL)
	= itmp			//
					;
	//test frame logic
	while(1)
	{
		itmp = *(int *)(MCASP0_BASE_ADD + MCASP_GBLCTL);
		if(itmp & ((0x1 << 12) + (0x1 << 4))) 
			break;