peripheral.h

实现了TI的C672x写列DSP的dMAX服务于MCASP的配置,

/*****************************************************************************
created by ckq;2007-3-16
file name : peripheral.h
*****************************************************************************/
/*CUP CONTROL REGISTERS*/
extern __cregister volatile unsigned int AMR;
extern __cregister volatile unsigned int CSR;
extern __cregister volatile unsigned int IFR;
extern __cregister volatile unsigned int ISR;
extern __cregister volatile unsigned int ICR;
extern __cregister volatile unsigned int IER;
extern __cregister volatile unsigned int ISTP;
extern __cregister volatile unsigned int IRP;
extern __cregister volatile unsigned int NRP;

//#ifdef _TMS320C6700
extern __cregister volatile unsigned int FADCR;
extern __cregister volatile unsigned int FAUCR;
extern __cregister volatile unsigned int FMCR;
//#endif

//#ifdef _TMS320C6700_PLUS
extern __cregister volatile unsigned int DESR;
extern __cregister volatile unsigned int DETR;
//#endif

//Device configuration register
#define	DEVICE_CONTREG_CFGBRIDGE	0x40000024
//

/*MCASP*/
/***********DEFINE THE MCASP REGISTER'S ADDRESS*****************/
#define MCASP0_BASE_ADD 0x44000000
#define MCASP1_BASE_ADD 0x45000000

#define MCASP_PID 0x0
#define MCASP_PWRDEMU 0x4
#define MCASP_PFUNC 0x10
#define MCASP_PDIR 0x14
#define MCASP_PDOUT 0x18
#define MCASP_PDIN 0x1C
#define MCASP_PDSET 0x1C
#define MCASP_PDCLR 0x20
#define MCASP_GBLCTL 0x44
#define MCASP_AMUTE 0x48
#define MCASP_DLBCTL 0x4C
#define MCASP_DITCTL 0x50
#define MCASP_RGBLCTL 0x60
#define MCASP_RMASK 0x64
#define MCASP_RFMT 0x68
#define MCASP_AFSRCTL 0x6C
#define MCASP_ACLKRCTL 0x70
#define MCASP_AHCLKRCTL 0x74
#define MCASP_RTDM 0x78
#define MCASP_RINTCTL 0x7C
#define MCASP_RSTAT 0x80
#define MCASP_RSLOT 0x84
#define MCASP_RCLKCHK 0x88
#define MCASP_REVTCTL 0x8C
#define MCASP_XGBLCTL 0xA0
#define MCASP_XMASK 0xA4
#define MCASP_XFMT 0xA8
#define MCASP_AFSXCTL 0xAC
#define MCASP_ACLKXCTL 0xB0
#define MCASP_AHCLKXCTL 0xB4
#define MCASP_XTDM 0xB8
#define MCASP_XINTCTL 0xBC
#define MCASP_XSTAT 0xC0
#define MCASP_XSLOT 0xC4
#define MCASP_XCLKCHK 0xC8
#define MCASP_XEVTCTL 0xCC
#define MCASP_SRCTL0 0x180
#define MCASP_SRCTL1 0x184
#define MCASP_SRCTL2 0x188
#define MCASP_SRCTL3 0x18C
#define MCASP_SRCTL4 0x190
#define MCASP_SRCTL5 0x194
#define MCASP_SRCTL6 0x198
#define MCASP_SRCTL7 0x19C
#define MCASP_SRCTL8 0x1A0
#define MCASP_SRCTL9 0x1A4
#define MCASP_SRCTL10 0x1A8
#define MCASP_SRCTL11 0x1AC
#define MCASP_SRCTL12 0x1B0
#define MCASP_SRCTL13 0x1B4
#define MCASP_SRCTL14 0x1B8
#define MCASP_SRCTL15 0x1BC

#define MCASP_XBUF0 0x200
#define MCASP_XBUF1 0x204
#define MCASP_XBUF2 0x208
#define MCASP_XBUF3 0x20C
#define MCASP_XBUF4 0x210
#define MCASP_XBUF5 0x214
#define MCASP_XBUF6 0x218
#define MCASP_XBUF7 0x21C
#define MCASP_XBUF8 0x220
#define MCASP_XBUF9 0x224
#define MCASP_XBUF10 0x228
#define MCASP_XBUF11 0x22C
#define MCASP_XBUF12 0x230
#define MCASP_XBUF13 0x234
#define MCASP_XBUF14 0x238
#define MCASP_XBUF15 0x23C

#define MCASP_RBUF0 0x280
#define MCASP_RBUF1 0x284
#define MCASP_RBUF2 0x288
#define MCASP_RBUF3 0x28C
#define MCASP_RBUF4 0x290
#define MCASP_RBUF5 0x294
#define MCASP_RBUF6 0x298
#define MCASP_RBUF7 0x29C
#define MCASP_RBUF8 0x2A0
#define MCASP_RBUF9 0x2A4
#define MCASP_RBUF10 0x2A8
#define MCASP_RBUF11 0x2AC
#define MCASP_RBUF12 0x2B0
#define MCASP_RBUF13 0x2B4
#define MCASP_RBUF14 0x2B8
#define MCASP_RBUF15 0x2BC

/*****************DEFINE THE dMAX REGISTER'S ADDRESS********************/
#define DMAX_CONTREG_BASE_ADD 	0x60000000

#define DMAX_DEPR		0x08
#define	DMAX_DEER		0x0C
#define DMAX_DEDR		0x10
#define	DMAX_DEHPR		0x14
#define	DMAX_DELPR		0x18
#define	DMAX_DEFR		0x1C
#define	DMAX_DER0		0x34
#define	DMAX_DER1		0x54
#define	DMAX_DER2		0x74
#define	DMAX_DER3		0x94
#define	DMAX_DFSR0		0x40
#define	DMAX_DFSR1		0x60
#define	DMAX_DTCR0		0x80
#define	DMAX_DTCR1		0xA0
//DMAX_DETR
//DMAX_DERR
//*****************DEFINE THE dMAX HiMAX Event Entry table START ADDRESS*****/
#define DMAX_HiMAX_EVENT_ENTRYADD 		0x61008000
//*****************DEFINE THE dMAX HiMAX Transfer Entry table START ADDRESS****/
#define DMAX_HiMAX_TRANSFER_ENTRYADD 	0x610080A0
//*****************DEFINE THE dMAX LoMAX Event Entry table START ADDRESS*****/
#define DMAX_LoMAX_EVENT_ENTRYADD 		0x62008000
//*****************DEFINE THE dMAX LoMAX Transfer Entry table START ADDRESS****/
#define DMAX_LoMAX_TRANSFER_ENTRYADD 	0x620080A0
/********************************************************************
end of file peripheral.h
********************************************************************/

//****************** EMIF Control Register *************************/
//External SDRAM base address on EMIF
#define EMIF_SDRAM_BASE_ADD			0x80000000
//External Asynchronous/Flash space on EMIF
#define EMIF_FLASH_BASE_ADD			0x90000000
//base address
#define EMIF_CONTREG_BASE_ADD		0xF0000000
//control registers offset
#define EMIF_CONTREG_AWCCR			0x00000004
#define EMIF_CONTREG_SDCR			0x00000008
#define EMIF_CONTREG_SDRCR			0x0000000C
#define EMIF_CONTREG_A1CR			0x00000010
#define EMIF_CONTREG_SDTIMR			0x00000020
#define EMIF_CONTREG_SDSRETR		0x0000003C
#define EMIF_CONTREG_EIRR			0x00000040
#define EMIF_CONTREG_EIMR			0x00000044
#define EMIF_CONTREG_EIMSR			0x00000048
#define EMIF_CONTREG_EIMCR			0x0000004C
#define EMIF_CONTREG_NANDFCR		0x00000060
#define EMIF_CONTREG_NANDFSR		0x00000064
#define EMIF_CONTREG_NANDF1ECC		0x00000070
//***************** SDRAM address*********************************/
//
#define	SDRAM_BASE_ADD				0x80000000
//
//****************** PLL Control Register*************************/
//base address
#define PLL_CONTREG_BASE_ADD		0x41000000
//control registers offset
#define PLL_CONTREG_PLLPID			0x00000000
#define PLL_CONTREG_PLLCSR			0x00000100
#define PLL_CONTREG_PLLM			0x00000110
#define PLL_CONTREG_PLLDIV0			0x00000114
#define PLL_CONTREG_PLLDIV1			0x00000118
#define PLL_CONTREG_PLLDIV2			0x0000011C
#define PLL_CONTREG_PLLDIV3			0x00000120
#define PLL_CONTREG_PLLCMD			0x00000138
#define PLL_CONTREG_PLLSTAT			0x0000013C
#define PLL_CONTREG_ALNCTL			0x00000140
#define PLL_CONTREG_CKEN			0x00000148
#define PLL_CONTREG_CKSTAT			0x0000014C
#define PLL_CONTREG_SYSTAT			0x00000150
//		
//********************* SPI register *******************************/			 
//base address
//SPI0
#define SPI_CONTREG_BASE_ADD0		0x47000000
//SPI1
#define SPI_CONTREG_BASE_ADD1		0x48000000		
//control registers offset
//SPI0 and SPI1
#define SPI_CONTREG_SPIGCR0			0x00000000
#define SPI_CONTREG_SPIGCR1			0x00000004
#define SPI_CONTREG_SPIINT0			0x00000008
#define SPI_CONTREG_SPILVL			0x0000000C
#define SPI_CONTREG_SPIFLG			0x00000010
#define SPI_CONTREG_SPIPC0			0x00000014
#define SPI_CONTREG_SPIPC1			0x00000018
#define SPI_CONTREG_SPIPC2			0x0000001C
#define SPI_CONTREG_SPIPC3			0x00000020
#define SPI_CONTREG_SPIPC4			0x00000024
#define SPI_CONTREG_SPIPC5			0x00000028
#define SPI_CONTREG_SPIDAT0			0x00000038
#define SPI_CONTREG_SPIDAT1			0x0000003C
#define SPI_CONTREG_SPIBUF			0x00000040
#define SPI_CONTREG_SPIEMU			0x00000044
#define SPI_CONTREG_SPIDELAY		0x00000048
#define SPI_CONTREG_SPIDEF			0x0000004C
#define SPI_CONTREG_SPIFMT0			0x00000050
#define SPI_CONTREG_SPIFMT1			0x00000054
#define SPI_CONTREG_SPIFMT2			0x00000058
#define SPI_CONTREG_SPIFMT3			0x0000005C
#define SPI_CONTREG_TGINTVECT0		0x00000060
#define SPI_CONTREG_TGINTVECT1		0x00000064