📄 dds.mdl
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Model {
Name "dds"
Version 5.0
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Mon Oct 06 09:03:03 2003"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "Administrator"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Wed Aug 11 17:15:57 2004"
ModelVersionFormat "1.%<AutoIncrement:67>"
ConfigurationManager "None"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "FixedStepDiscrete"
SolverMode "Auto"
StartTime "0.0"
StopTime "5.0"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "1e-3"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType on
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
RTWOptions "-aEnforceIntegerDowncast=1 -aExtMode=0 -aExtModeTes"
"ting=0 -aFoldNonRolledExpr=1 -aForceParamTrailComments=0 -aGenerateComments=1"
" -aGenerateReport=0 -aIgnoreCustomStorageClasses=1 -aIncDataTypeInIds=0 -aInc"
"HierarchyInIds=0 -aInlineInvariantSignals=0 -aInlinedPrmAccess=\"Literals\" -"
"aLocalBlockOutputs=1 -aLogVarNameModifier=\"rt_\" -aMaxRTWIdLen=31 -aPrefixMo"
"delToSubsysFcnNames=1 -aRTWVerbose=1 -aRollThreshold=5 -aShowEliminatedStatem"
"ents=0"
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Constant
Value "1"
VectorParams1D on
ShowAdditionalParam off
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
}
Block {
BlockType Inport
Port "1"
PortDimensions "-1"
SampleTime "-1"
ShowAdditionalParam off
LatchInput off
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
Interpolate on
}
Block {
BlockType Outport
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Scope
Floating off
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "0"
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "dds"
Location [2, 74, 1014, 728]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "AMP1"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [470, 262, 535, 278]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Internal Node"
bwl "16"
bwr "8"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "AMP1"
ppat "d:\\matlab6\\work\\gw48_sopc_1c6_demo\\dds_l\\D"
"SPBuilder_dds"
nSgCpl "1"
}
Block {
BlockType Reference
Name "AMPlify"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [470, 352, 535, 368]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Input Port"
bwl "8"
bwr "8"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "AMPlify"
ppat "d:\\matlab6\\work\\gw48_sopc_1c6_demo\\dds_l\\D"
"SPBuilder_dds"
nSgCpl "1"
}
Block {
BlockType Reference
Name "BusConcatenation"
Ports [2, 1]
Position [965, 570, 1080, 625]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConcatenation"
SourceType "Bus Concatenation AlteraBlockSet"
bwl "1"
bwr "9"
blean off
}
Block {
BlockType Reference
Name "BusConcatenation1"
Ports [2, 1]
Position [175, 176, 280, 214]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConcatenation"
SourceType "Bus Concatenation AlteraBlockSet"
bwl "8"
bwr "15"
blean off
}
Block {
BlockType Reference
Name "BusConcatenation6"
Ports [2, 1]
Position [330, 296, 435, 334]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConcatenation"
SourceType "Bus Concatenation AlteraBlockSet"
bwl "9"
bwr "23"
blean off
}
Block {
BlockType "S-Function"
Name "BusConversion"
Ports [1, 1]
Position [790, 597, 870, 623]
ForegroundColor "blue"
AncestorBlock "bus_alteradspbuilder/BusConversion"
FunctionName "SExtractBus"
Parameters "-1 Inputs bwl bwr Outputs obwl obwr msb lsb rnd"
" sat"
MaskType "SubBus Altera BlockSet"
MaskDescription "BusConversion\n\nExtract a subsection of a bus."
" Supports bus type and width conversion.\n\nUsage: \n\n1. Choose the input an"
"d output bus types you wish to use and click\n Apply. Different options ar"
"e available for each bus type.\n2. Make additional settings as needed.\n3. Cl"
"ick OK."
MaskHelp "web([GETDOCPATH(0) 'busman-busconv.html'])"
MaskPromptString "Input Bus Type |Input [number of bits].[] |Inpu"
"t [].[number of bits] |Output Bus Type |Output [number of bits].[] |Output ["
"].[number of bits] |Input Bit Connected to Output MSB |Input Bit Connect"
"ed to Output LSB |Round|Saturate"
MaskStyleString "popup(Signed Integer|Signed Fractional|Unsigned"
" Integer),popup(1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|2"
"4|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47|48|49|"
"50|51),popup(0|1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|24"
"|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47|48|49|5"
"0|51),popup(Signed Integer|Signed Fractional|Unsigned Integer),popup(1|2|3|4|"
"5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|3"
"2|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47|48|49|50|51),popup(0|1|2|3|4|5"
"|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32"
"|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47|48|49|50|51),popup(0|1|2|3|4|5|"
"6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|"
"33|34|35|36|37|38|39|40|41|42|43|44|45|46|47|48|49|50|51),popup(0|1|2|3|4|5|6"
"|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|3"
"3|34|35|36|37|38|39|40|41|42|43|44|45|46|47|48|49|50|51),checkbox,checkbox"
MaskTunableValueString "on,on,on,on,on,on,on,on,on,on"
MaskCallbackString "|||||||||"
MaskEnableString "on,on,on,on,on,on,on,on,on,on"
MaskVisibilityString "on,on,off,on,on,off,on,on,on,on"
MaskToolTipString "on,on,on,on,on,on,on,on,on,on"
MaskVarAliasString ",,,,,,,,,"
MaskVariables "Inputs=@1;bwl=@2;bwr=@3;Outputs=@4;obwl=@5;obwr"
"=@6;msb=@7;lsb=@8;rnd=@9;sat=@10;"
MaskInitialization "[iwth owth visib]=busconinit(Inputs,Outputs,bwl"
", bwr ,obwl, obwr,msb,lsb);\nset_param(gcb,'MaskVisibilities',visib);\n\n\n"
MaskDisplay "plot([0 0 20 20 40 40],[10 0 0 20 20 10])\nfpr"
"intf('%s %s',iwth,owth)"
MaskIconFrame off
MaskIconOpaque on
MaskIconRotate "port"
MaskIconUnits "autoscale"
MaskValueString "Signed Integer|10|8|Signed Integer|9|0|8|0|off|"
"off"
}
Block {
BlockType Reference
Name "BusConversion1"
Ports [1, 1]
Position [935, 241, 1010, 259]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConversion"
SourceType "SubBus Altera BlockSet"
Inputs "Unsigned Integer"
bwl "10"
bwr "8"
Outputs "Unsigned Integer"
obwl "8"
obwr "0"
msb "9"
lsb "2"
rnd off
sat off
}
Block {
BlockType Constant
Name "Constant1"
Position [30, 170, 60, 200]
Value "90"
}
Block {
BlockType Constant
Name "Constant2"
Position [400, 370, 430, 400]
Value "253"
}
Block {
BlockType Reference
Name "Constant4"
Description "Sign Binary Fractionnal"
Ports [0, 1]
Position [70, 231, 120, 249]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Constant"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Constant"
bwl "15"
bwr "8"
sat off
rnd off
bp off
mask_cst "0"
ncstsamp "-1"
cst "0"
modulename "Constant4"
ppat "d:\\matlab6\\work\\gw48_sopc_1c6_demo\\dds_l\\D"
"SPBuilder_dds"
nSgCpl "1"
}
Block {
BlockType Reference
Name "Constant6"
Description "Sign Binary Fractionnal"
Ports [0, 1]
Position [230, 281, 280, 299]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Constant"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Constant"
bwl "9"
bwr "8"
sat off
rnd off
bp off
mask_cst "0"
ncstsamp "-1"
cst "0"
modulename "Constant6"
ppat "d:\\matlab6\\work\\gw48_sopc_1c6_demo\\dds_l\\D"
"SPBuilder_dds"
nSgCpl "1"
}
Block {
BlockType Reference
Name "Constant7"
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