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<title>DSP Builder Report File</title>
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<h3>DSP Builder Report File for dds.mdl</h3>
<hr><h3>Project Setting</h3><TABLE>
<TR>
<TD><b>Device Family</b> </TD> <TD>ACEX1K</TD>
</TR>
<TR>
<TD><b>Synthesis Tool</b> </TD> <TD>Quartus II</TD>
</TR>
<TR>
<TD> <b>Optimization </b></TD> <TD>Speed</TD>
</TR>
<TR>
<TD> <b>Date</b> </TD> <TD>Wednesday, August 11, 2004</TD>
</TR>
<TR>
<TD> <b>Time</b> </TD> <TD>17:15:12</TD>
</TR>
<TR>
<TD><b>Version</b> </TD> <TD> 2.1.3 Build 31</TD>
</TR>
</TABLE>
<hr>
<h3>Compilation </h3>
<TABLE>
<TR>
<TD>Convert Mdl to VHDL </TD> <TD><b>:</b> PASSED </TD><TD></TD>
</TR>
<TR>
<TD>Synthesis </TD> <TD><b>:</b> PASSED </TD><TD></TD>
</TR>
<TR>
<TD>Quartus II Fitter</TD> <TD><b>:</b> --------- </TD><TD></TD>
</TR>
</TABLE>
<hr>
<h3>Resource Utilization</h3><table><TR><TD>Logic Cells </TD><TD>: 268</TD></TR><TR><TD>Registers</TD><TD>: 83</TD></TR><TR><TD>Pins</TD><TD>: 134</TD></TR><TR><TD>Memory Bits</TD><TD>: 10240</TD></TR><TR><TD>DSP Elements</TD><TD>: 27</TD></TR></TABLE><hr>
<!--<h3>Timing Information</h3>-->
<h3>Input Output Pin Information</h3><TABLE>
<TR><TD><b>Pin name </b></TD>
<TD><b>Pin Direction </b></TD>
<TD><b>Bus Type </b></TD></TR>
<TR><TD> clock </TD><TD> in </TD><TD>std_logic</TD></TR><TR><TD> sclrp </TD><TD> in </TD><TD>std_logic</TD></TR><TR><TD> iAMPlifys </TD><TD> in </TD><TD>std_logic_vector(7 downto 0)</TD></TR><TR><TD> iFREQWORDs </TD><TD> in </TD><TD>std_logic_vector(7 downto 0)</TD></TR><TR><TD> oDA_CSs </TD><TD> out </TD><TD>std_logic</TD></TR><TR><TD> oDA_DATAs </TD><TD> out </TD><TD>std_logic_vector(7 downto 0)</TD></TR><TR><TD></TR></TABLE><br>
<p><b>Clock input pin :</b> All registered blocks use the input clock signal <b>'clock'</b>. dds.mdl does not use PLL.<br><b>Reset input pin :</b> All registered blocks use the global reset input signal <b>'sclrp'</b> , which is synchronous and active high</p><hr>
<h3>Files Generated by SignalCompiler</h3><TABLE BORDER>
<TR>
<TD> <b>dds.vhd</b> </TD><TD>VHDL representation of the design for synthesis and simulation </TD>
</TR>
<TR>
<TD> <b>SubDDS.vhd</b> </TD><TD>VHDL hierarchy for synthesis and simulation </TD>
</TR>
<TR>
</TR>
<TR>
<TD> <b>dds_quartus.tcl</b> </TD><TD>Tcl script for Quartus<font size="-1"><sup>®</font></sup> II compilation. <p><I>When compiling the design manually in the Quartus II software, type </i><b>source dds_quartus.tcl </b><i> in the Quartus II tcl console (Auxiliary Windows). The Quartus II software executes the Tcl script that sets up the project and environment for your design.</I></p></TD>
</TR>
<TR>
<TD> <b>dds.vec</b> </TD><TD>Quartus<font size="-1"><sup>®</font></sup> II simulation vector file </TD>
</TR>
<TR>
<TD><b> tb_dds.vhd</b> </TD><TD>VHDL design testbench for simulation </TD>
</TR>
<TR>
<TD> <b>tb_dds.tcl</b> </TD><TD>Tcl script for ModelSim simulation <p><I>type </i><b>do tb_dds.tcl </b><i> at Modelsim prompt.</p></TD>
</TR>
<TR>
<TD><b> tb_dds.v</b> </TD><TD>Verilog design testbench for simulation with Quartus II Verilog Output File (.vo)</TD>
</TR>
</TABLE><br>
<hr>
<h3>Synthesis & Compilation Log Files</h3>
<!--<p><A HREF="dds.srr">Synplicity Log</A></p>-->
<!--<p><A HREF="exemplar.log">Leonardo Log</A></p>-->
<p><A HREF="dds.map.rpt">Quartus II Map Log</A></p>
<!--<p><A HREF="dds.fit.rpt">Quartus II Fit Log</A></p>-->
<hr>
<h3>Entity dds</h3>
<p><A HREF="DSPBuilder_dds\ddsblockInfos.html">Information page</A> on the DSP Builder blocks used in dds.</p>
<h4>Hierarchy Information</h4>
<p>
This section lists the "Hdl Sub-System" block used in the design (Black Box and VHDL)
with the number of instance of those blocks accross the hierarchy branches.
</p>
<TABLE>
<TR>
<TD><a href="#SubDDS"> SubDDS <a></TD> <TD> 1 </TD>
</TR>
</TABLE>
<p><i>VHDL SubSystem </i> :
Each "Hdl Sub-System" map to a unique VHDL entity generated on-the-fly by SignalCompiler, and therefore must
be uniquified in Simulink.
Make sure that "Hdl Sub-System" block with identical names have the
exact same functionality
</p><p><i>Black Box SubSystem</i> :
A Black Box SubSystem is used to import VHDL design into the design using the HDL SubSystem mechanism. SignalCompiler generates only the black component declaration and mapping. For clock signals, SignalCompiler will connect automatically to the global "clock" signal of the design the signal of the black box which has the instance name "simulink_clock"</p>
<h4>Bus width extension</h4><p> In order to maintain bit accuracy between the Simulink domain and the VHDL domain, the MDL to VHDL conversion process may extend or reduce bus width. This occurs <table><tr><td>- When the block input port bit width is greater than the signal input port bit width, SignalCompiler sign extends the signal bit width to the input port bit width.</td></tr><tr><td>- When the block input port bit width is smaller than the signal input port bit width, SignalCompiler truncates the signal bit width to the input port bit width.</td></tr><tr><td>- For designs in which unsigned integer signals are used in Simulink, SignalCompiler translates the Simulink unsigned bus type with width w into a VHDL signed bus of width w + 1 where the MSB bit is stuck to 0.</td></tr></table></p><pre> "SubDDS" : input port "iamps" [8].[0] is driven by a signal [9].[0].
</pre><h4>Warning Section</h4><p>
<b> Signals Out of Range </b>: This section lists the signals with a bit width greater than 51 bits. Fixed-point DSP Builder models support up to 51 bits of resolution. When the bit width grows over 51 bits, additional VHDL RTL simulations are recommended to estimate the effect of overflow and rounding introduced by double signals.</p><pre>>Warning : Bus width greater than 51 bits
Block BusConcatenation1: Bit width mismatch for input port 1
Expect 8 bits instead of 9 bitsBlock BusConcatenation1: Bit width mismatch for input port 1
Expect 15 bits instead of 16 bitsBlock BusConcatenation6: Bit width mismatch for input port 1
Expect 9 bits instead of 10 bitsBlock BusConcatenation6: Bit width mismatch for input port 1
Expect 23 bits instead of 24 bits
</pre>
<hr>
<a name="SubDDS"> </a>
<h3>Entity SubDDS</h3>
<p><A HREF="DSPBuilder_dds\SubDDSblockInfos.html">Information page</A> on the DSP Builder blocks used in SubDDS.</p>
<h4>Warning Section</h4><h4>Bus width extension</h4><p> In order to maintain bit accuracy between the Simulink domain and the VHDL domain, the MDL to VHDL conversion process may extend or reduce bus width. This occurs <table><tr><td>- When the block input port bit width is greater than the signal input port bit width, SignalCompiler sign extends the signal bit width to the input port bit width.</td></tr><tr><td>- When the block input port bit width is smaller than the signal input port bit width, SignalCompiler truncates the signal bit width to the input port bit width.</td></tr><tr><td>- For designs in which unsigned integer signals are used in Simulink, SignalCompiler translates the Simulink unsigned bus type with width w into a VHDL signed bus of width w + 1 where the MSB bit is stuck to 0.</td></tr></table></p><pre> "BusConversion2" : input port "xin " [32].[0] is driven by a signal [33].[0].
"BusConversion3" : input port "xin " [18].[0] is driven by a signal [19].[0].
</pre><hr>
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<TD> </TD><TD align="right"> <A HREF="D:\MATLAB6\DSPBuilder\Altlib\..\doc\dsp_builder_ugTOC.html">help</A></TD>
</TR></TABLE><hr>
DSP Builder <br>Quartus II development tool and MATLAB/Simulink Interface
<br>Version 2.1.3 Build 31<p>Copyright © 2001-2003 Altera Corporation. All rights reserved.</p>
<p>The DSP Builder software, including, without limitation, the clock-cycle limited
versions of the MegaCore® Logic Functions included therein, may only be used to
develop designs for programmable logic devices manufactured by Altera Corporation
and sold by Altera Corporation and its authorized distributors. IN NO EVENT MAY
SUCH SOFTWARE AND FUNCTIONS BE USED TO PROGRAM ANY PROGRAMMABLE LOGIC DEVICES, FIELD
PROGRAMMABLE GATE ARRAYS, ASICS, STANDARD PRODUCTS, OR ANY OTHER SEMICONDUCTOR
DEVICE MANUFACTURED BY ANY COMPANY OR ENTITY OTHER THAN ALTERA. For the complete
terms and conditions applicable to your use of the software and functions, please
refer to the Altera Program License.</p>
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