dds.map.eqn

DDS的DSP实现

N12_cs_buffer[7] = N51_sout_node[5] $ N21_sout_node[9] $ N12_cout[6];

--N12_cout[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

N12_cout[7] = CARRY(N51_sout_node[5] & (N21_sout_node[9] # N12_cout[6]) # !N51_sout_node[5] & N21_sout_node[9] & N12_cout[6]);


--N42_cs_buffer[2] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

N42_cs_buffer[2] = N81_sout_node[0] $ N12_cs_buffer[6] $ N42_cout[1];

--N42_cout[2] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

N42_cout[2] = CARRY(N81_sout_node[0] & (N12_cs_buffer[6] # N42_cout[1]) # !N81_sout_node[0] & N12_cs_buffer[6] & N42_cout[1]);


--N9_cs_buffer[7] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic

N9_cs_buffer[7] = N42_cs_buffer[1] $ N9_cout[6];

--N9_cout[7] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

N9_cout[7] = CARRY(N42_cs_buffer[1] & N9_cout[6]);


--Q1_q[7] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[7]
Q1_q[7]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[7]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[7] = MEMORY_SEGMENT(, , , , , , , , Q1_q[7]_write_address, Q1_q[7]_read_address);


--N72_cs_buffer[7] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic

N72_cs_buffer[7] = E1L8Q $ H1L9Q $ N72_cout[6];

--N72_cout[7] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

N72_cout[7] = CARRY(E1L8Q & (H1L9Q # N72_cout[6]) # !E1L8Q & H1L9Q & N72_cout[6]);


--N72_cs_buffer[8] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]
--operation mode is arithmetic

N72_cs_buffer[8] = H1L01Q $ N72_cout[7];

--N72_cout[8] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

N72_cout[8] = CARRY(H1L01Q & N72_cout[7]);


--N72_cs_buffer[9] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]
--operation mode is arithmetic

N72_cs_buffer[9] = H1L11Q $ N72_cout[8];

--N72_cout[9] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

N72_cout[9] = CARRY(H1L11Q & N72_cout[8]);


--N72_cs_buffer[10] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]
--operation mode is arithmetic

N72_cs_buffer[10] = H1L21Q $ N72_cout[9];

--N72_cout[10] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

N72_cout[10] = CARRY(H1L21Q & N72_cout[9]);


--N72_cs_buffer[11] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]
--operation mode is arithmetic

N72_cs_buffer[11] = H1L31Q $ N72_cout[10];

--N72_cout[11] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

N72_cout[11] = CARRY(H1L31Q & N72_cout[10]);


--N72_cs_buffer[12] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]
--operation mode is arithmetic

N72_cs_buffer[12] = H1L41Q $ N72_cout[11];

--N72_cout[12] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12]
--operation mode is arithmetic

N72_cout[12] = CARRY(H1L41Q & N72_cout[11]);


--N72_cs_buffer[13] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]
--operation mode is arithmetic

N72_cs_buffer[13] = H1L51Q $ N72_cout[12];

--N72_cout[13] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

N72_cout[13] = CARRY(H1L51Q & N72_cout[12]);


--N72_cs_buffer[14] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]
--operation mode is arithmetic

N72_cs_buffer[14] = H1L61Q $ N72_cout[13];

--N72_cout[14] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14]
--operation mode is arithmetic

N72_cout[14] = CARRY(H1L61Q & N72_cout[13]);


--N72_cs_buffer[15] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]
--operation mode is arithmetic

N72_cs_buffer[15] = H1L71Q $ N72_cout[14];

--N72_cout[15] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15]
--operation mode is arithmetic

N72_cout[15] = CARRY(H1L71Q & N72_cout[14]);


--N21_sout_node[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|sout_node[9]
--operation mode is arithmetic

N21_sout_node[9]_lut_out = N21_cout[8] $ (T2L1 # T11L41);
N21_sout_node[9] = DFFEA(N21_sout_node[9]_lut_out, clock, !sclrp, , , , );

--N21_cout[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

N21_cout[9] = CARRY(N21_cout[8] & (T2L1 # T11L41));


--Q1_q[6] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[6]
Q1_q[6]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[6]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[6] = MEMORY_SEGMENT(, , , , , , , , Q1_q[6]_write_address, Q1_q[6]_read_address);


--Q1_q[5] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[5]
Q1_q[5]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[5]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[5] = MEMORY_SEGMENT(, , , , , , , , Q1_q[5]_write_address, Q1_q[5]_read_address);


--Q1_q[4] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[4]
Q1_q[4]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[4]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[4] = MEMORY_SEGMENT(, , , , , , , , Q1_q[4]_write_address, Q1_q[4]_read_address);


--Q1_q[3] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[3]
Q1_q[3]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[3]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[3] = MEMORY_SEGMENT(, , , , , , , , Q1_q[3]_write_address, Q1_q[3]_read_address);


--Q1_q[2] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[2]
Q1_q[2]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[2]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[2] = MEMORY_SEGMENT(, , , , , , , , Q1_q[2]_write_address, Q1_q[2]_read_address);


--T61L9 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[8]~154
--operation mode is normal

T61L9 = (G1_databint[5] & (G1_databint[6] # G1_dataaint[9] $ !G1_databint[7]) # !G1_databint[5] & (G1_dataaint[9] $ !G1_databint[7] # !G1_databint[6])) & CASCADE(T61L81);


--T61L81 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[8]~117
--operation mode is normal

T61L81 = G1_dataaint[8] & (G1_databint[7] # !G1_databint[6] # !G1_databint[5]) # !G1_dataaint[8] & (G1_databint[5] # G1_databint[6] # !G1_databint[7]);


--H1L8Q is SubDDS:SubDDSi|SAdderSub:u9|result[21]~reg0
--operation mode is normal

H1L8Q_lut_out = N72_cs_buffer[6] & !sclrp;
H1L8Q = DFFEA(H1L8Q_lut_out, clock, , , , , );


--H1L1 is SubDDS:SubDDSi|SAdderSub:u9|i108~0
--operation mode is normal

H1L1 = L9_unreg_res_node[16] & !sclrp;


--T61L8 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[7]~155
--operation mode is normal

T61L8 = (G1_dataaint[8] & (G1_databint[7] # G1_databint[5] $ !G1_databint[6]) # !G1_dataaint[8] & (G1_databint[5] $ !G1_databint[6] # !G1_databint[7])) & CASCADE(T61L71);


--T61L71 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[7]~118
--operation mode is normal

T61L71 = G1_dataaint[7] & (G1_databint[7] # !G1_databint[6] # !G1_databint[5]) # !G1_dataaint[7] & (G1_databint[5] # G1_databint[6] # !G1_databint[7]);


--T61L7 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[6]~156
--operation mode is normal

T61L7 = (G1_dataaint[7] & (G1_databint[7] # G1_databint[5] $ !G1_databint[6]) # !G1_dataaint[7] & (G1_databint[5] $ !G1_databint[6] # !G1_databint[7])) & CASCADE(T61L61);


--T61L61 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[6]~119
--operation mode is normal

T61L61 = G1_dataaint[6] & (G1_databint[7] # !G1_databint[6] # !G1_databint[5]) # !G1_dataaint[6] & (G1_databint[5] # G1_databint[6] # !G1_databint[7]);


--T61L6 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[5]~157
--operation mode is normal

T61L6 = (G1_dataaint[6] & (G1_databint[7] # G1_databint[5] $ !G1_databint[6]) # !G1_dataaint[6] & (G1_databint[5] $ !G1_databint[6] # !G1_databint[7])) & CASCADE(T61L51);


--T61L51 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[5]~120
--operation mode is normal

T61L51 = G1_dataaint[5] & (G1_databint[7] # !G1_databint[6] # !G1_databint[5]) # !G1_dataaint[5] & (G1_databint[5] # G1_databint[6] # !G1_databint[7]);


--T61L5 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[4]~158
--operation mode is normal

T61L5 = (G1_dataaint[5] & (G1_databint[7] # G1_databint[5] $ !G1_databint[6]) # !G1_dataaint[5] & (G1_databint[5] $ !G1_databint[6] # !G1_databint[7])) & CASCADE(T61L41);


--T61L41 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[4]~121
--operation mode is normal

T61L41 = G1_dataaint[4] & (G1_databint[7] # !G1_databint[6] # !G1_databint[5]) # !G1_dataaint[4] & (G1_databint[5] # G1_databint[6] # !G1_databint[7]);


--T61L4 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[3]~159
--operation mode is normal

T61L4 = (G1_dataaint[4] & (G1_databint[7] # G1_databint[5] $ !G1_databint[6]) # !G1_dataaint[4] & (G1_databint[5] $ !G1_databint[6] # !G1_databint[7])) & CASCADE(T61L31);


--T61L31 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[3]~122
--operation mode is normal

T61L31 = G1_dataaint[3] & (G1_databint[7] # !G1_databint[6] # !G1_databint[5]) # !G1_dataaint[3] & (G1_databint[5] # G1_databint[6] # !G1_databint[7]);


--G1_dataaint[1] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[1]
--operation mode is normal

G1_dataaint[1]_lut_out = Q1_q[1] & !sclrp;
G1_dataaint[1] = DFFEA(G1_dataaint[1]_lut_out, clock, , , , , );


--T21L1 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[0]~0
--operation mode is normal

T21L1 = G1_dataaint[1] & G1_databint[7];


--N81_sout_node[0] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[0]
--operation mode is arithmetic

N8