dds.map.eqn

DDS的DSP实现

N42_cs_buffer[3] = N81_sout_node[1] $ N12_cs_buffer[7] $ N42_cout[2];

--N42_cout[3] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

N42_cout[3] = CARRY(N81_sout_node[1] & (N12_cs_buffer[7] # N42_cout[2]) # !N81_sout_node[1] & N12_cs_buffer[7] & N42_cout[2]);


--N9_cs_buffer[8] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]
--operation mode is arithmetic

N9_cs_buffer[8] = N42_cs_buffer[2] $ N9_cout[7];

--N9_cout[8] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

N9_cout[8] = CARRY(N42_cs_buffer[2] & N9_cout[7]);


--Q1_q[8] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[8]
Q1_q[8]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[8]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[8] = MEMORY_SEGMENT(, , , , , , , , Q1_q[8]_write_address, Q1_q[8]_read_address);


--H1L81Q is SubDDS:SubDDSi|SAdderSub:u9|result[31]~reg0
--operation mode is arithmetic

H1L81Q_lut_out = H1L1;
H1L81Q = DFFEA(H1L81Q_lut_out, clock, , , , , );

--N3_cout[0] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

N3_cout[0] = CARRY(!H1L81Q);


--L1_unreg_res_node[31] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[31]
--operation mode is normal

L1_unreg_res_node[31] = N3_cout[30] $ H1L81Q;


--N51_sout_node[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[10]
--operation mode is arithmetic

N51_sout_node[10]_lut_out = T6L1 $ T4L1 $ N51_cout[9];
N51_sout_node[10] = DFFEA(N51_sout_node[10]_lut_out, clock, !sclrp, , , , );

--N51_cout[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

N51_cout[10] = CARRY(T6L1 & (T4L1 # N51_cout[9]) # !T6L1 & T4L1 & N51_cout[9]);


--T2L2 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:$00034|right_bit[0]~0
--operation mode is normal

T2L2 = G1_databint[1] & !G1_databint[0] & !G1_dataaint[9];


--T2L1 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:$00034|left_bit[0]~45
--operation mode is normal

T2L1 = G1_databint[0] & (G1_databint[1] $ G1_dataaint[9]);


--N21_sout_node[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|sout_node[10]
--operation mode is arithmetic

N21_sout_node[10]_lut_out = N21_cout[9] $ (T2L2 # T2L1);
N21_sout_node[10] = DFFEA(N21_sout_node[10]_lut_out, clock, !sclrp, , , , );

--N21_cout[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

N21_cout[10] = CARRY(N21_cout[9] & (T2L2 # T2L1));


--G1_dataaint[7] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[7]
--operation mode is normal

G1_dataaint[7]_lut_out = Q1_q[7] & !sclrp;
G1_dataaint[7] = DFFEA(G1_dataaint[7]_lut_out, clock, , , , , );


--T21L7 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[6]~6
--operation mode is normal

T21L7 = G1_dataaint[7] & G1_databint[7];


--H1L9Q is SubDDS:SubDDSi|SAdderSub:u9|result[22]~reg0
--operation mode is normal

H1L9Q_lut_out = N72_cs_buffer[7] & !sclrp;
H1L9Q = DFFEA(H1L9Q_lut_out, clock, , , , , );


--H1L01Q is SubDDS:SubDDSi|SAdderSub:u9|result[23]~reg0
--operation mode is normal

H1L01Q_lut_out = N72_cs_buffer[8] & !sclrp;
H1L01Q = DFFEA(H1L01Q_lut_out, clock, , , , , );


--H1L11Q is SubDDS:SubDDSi|SAdderSub:u9|result[24]~reg0
--operation mode is normal

H1L11Q_lut_out = N72_cs_buffer[9] & !sclrp;
H1L11Q = DFFEA(H1L11Q_lut_out, clock, , , , , );


--H1L21Q is SubDDS:SubDDSi|SAdderSub:u9|result[25]~reg0
--operation mode is normal

H1L21Q_lut_out = N72_cs_buffer[10] & !sclrp;
H1L21Q = DFFEA(H1L21Q_lut_out, clock, , , , , );


--H1L31Q is SubDDS:SubDDSi|SAdderSub:u9|result[26]~reg0
--operation mode is normal

H1L31Q_lut_out = N72_cs_buffer[11] & !sclrp;
H1L31Q = DFFEA(H1L31Q_lut_out, clock, , , , , );


--H1L41Q is SubDDS:SubDDSi|SAdderSub:u9|result[27]~reg0
--operation mode is normal

H1L41Q_lut_out = N72_cs_buffer[12] & !sclrp;
H1L41Q = DFFEA(H1L41Q_lut_out, clock, , , , , );


--H1L51Q is SubDDS:SubDDSi|SAdderSub:u9|result[28]~reg0
--operation mode is normal

H1L51Q_lut_out = N72_cs_buffer[13] & !sclrp;
H1L51Q = DFFEA(H1L51Q_lut_out, clock, , , , , );


--H1L61Q is SubDDS:SubDDSi|SAdderSub:u9|result[29]~reg0
--operation mode is normal

H1L61Q_lut_out = N72_cs_buffer[14] & !sclrp;
H1L61Q = DFFEA(H1L61Q_lut_out, clock, , , , , );


--H1L71Q is SubDDS:SubDDSi|SAdderSub:u9|result[30]~reg0
--operation mode is normal

H1L71Q_lut_out = N72_cs_buffer[15] & !sclrp;
H1L71Q = DFFEA(H1L71Q_lut_out, clock, , , , , );


--G1_dataaint[6] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[6]
--operation mode is normal

G1_dataaint[6]_lut_out = Q1_q[6] & !sclrp;
G1_dataaint[6] = DFFEA(G1_dataaint[6]_lut_out, clock, , , , , );


--T21L6 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[5]~5
--operation mode is normal

T21L6 = G1_dataaint[6] & G1_databint[7];


--G1_dataaint[5] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[5]
--operation mode is normal

G1_dataaint[5]_lut_out = Q1_q[5] & !sclrp;
G1_dataaint[5] = DFFEA(G1_dataaint[5]_lut_out, clock, , , , , );


--T21L5 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[4]~4
--operation mode is normal

T21L5 = G1_dataaint[5] & G1_databint[7];


--N51_sout_node[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[9]
--operation mode is arithmetic

N51_sout_node[9]_lut_out = T51L9 $ T4L1 $ !N51_cout[8];
N51_sout_node[9] = DFFEA(N51_sout_node[9]_lut_out, clock, !sclrp, , , , );

--N51_cout[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

N51_cout[9] = CARRY(T51L9 & T4L1 & N51_cout[8] # !T51L9 & (T4L1 # N51_cout[8]));


--G1_dataaint[4] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[4]
--operation mode is normal

G1_dataaint[4]_lut_out = Q1_q[4] & !sclrp;
G1_dataaint[4] = DFFEA(G1_dataaint[4]_lut_out, clock, , , , , );


--T21L4 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[3]~3
--operation mode is normal

T21L4 = G1_dataaint[4] & G1_databint[7];


--N51_sout_node[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[8]
--operation mode is arithmetic

N51_sout_node[8]_lut_out = T51L8 $ T4L1 $ !N51_cout[7];
N51_sout_node[8] = DFFEA(N51_sout_node[8]_lut_out, clock, !sclrp, , , , );

--N51_cout[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

N51_cout[8] = CARRY(T51L8 & T4L1 & N51_cout[7] # !T51L8 & (T4L1 # N51_cout[7]));


--G1_dataaint[3] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[3]
--operation mode is normal

G1_dataaint[3]_lut_out = Q1_q[3] & !sclrp;
G1_dataaint[3] = DFFEA(G1_dataaint[3]_lut_out, clock, , , , , );


--T21L3 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[2]~2
--operation mode is normal

T21L3 = G1_dataaint[3] & G1_databint[7];


--N51_sout_node[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[7]
--operation mode is arithmetic

N51_sout_node[7]_lut_out = T51L7 $ T41L9 $ N51_cout[6];
N51_sout_node[7] = DFFEA(N51_sout_node[7]_lut_out, clock, !sclrp, , , , );

--N51_cout[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

N51_cout[7] = CARRY(T51L7 & !T41L9 & N51_cout[6] # !T51L7 & (N51_cout[6] # !T41L9));


--G1_dataaint[2] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[2]
--operation mode is normal

G1_dataaint[2]_lut_out = Q1_q[2] & !sclrp;
G1_dataaint[2] = DFFEA(G1_dataaint[2]_lut_out, clock, , , , , );


--T21L2 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[1]~1
--operation mode is normal

T21L2 = G1_dataaint[2] & G1_databint[7];


--N81_sout_node[1] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[1]
--operation mode is arithmetic

N81_sout_node[1]_lut_out = T61L3 $ T21L1 $ !N81_cout[0];
N81_sout_node[1] = DFFEA(N81_sout_node[1]_lut_out, clock, !sclrp, , , , );

--N81_cout[1] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

N81_cout[1] = CARRY(T61L3 & T21L1 & N81_cout[0] # !T61L3 & (T21L1 # N81_cout[0]));


--N51_sout_node[6] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[6]
--operation mode is arithmetic

N51_sout_node[6]_lut_out = T51L6 $ T41L8 $ N51_cout[5];
N51_sout_node[6] = DFFEA(N51_sout_node[6]_lut_out, clock, !sclrp, , , , );

--N51_cout[6] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

N51_cout[6] = CARRY(T51L6 & !T41L8 & N51_cout[5] # !T51L6 & (N51_cout[5] # !T41L8));


--N12_cs_buffer[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic