dds.map.eqn

DDS的DSP实现

T4L1 = G1_dataaint[9] & !G1_databint[3] & (G1_databint[2] # G1_databint[1]) # !G1_dataaint[9] & G1_databint[3] & (!G1_databint[1] # !G1_databint[2]);


--G1_databint[4] is SubDDS:SubDDSi|AltiMult:Product1i|databint[4]
--operation mode is normal

G1_databint[4]_lut_out = iAMPlifys[4] & !sclrp;
G1_databint[4] = DFFEA(G1_databint[4]_lut_out, clock, , , , , );


--T6L1 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:$00042|out_bit[0]~0
--operation mode is normal

T6L1 = G1_dataaint[9] & !G1_databint[5] & (G1_databint[4] # G1_databint[3]) # !G1_dataaint[9] & G1_databint[5] & (!G1_databint[3] # !G1_databint[4]);


--N21_sout_node[12] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|sout_node[12]
--operation mode is normal

N21_sout_node[12]_lut_out = N21_cout[11] $ (G1_databint[1] & !G1_dataaint[9] # !G1_databint[1] & G1_dataaint[9] & G1_databint[0]);
N21_sout_node[12] = DFFEA(N21_sout_node[12]_lut_out, clock, !sclrp, , , , );


--N21_sout_node[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|sout_node[11]
--operation mode is arithmetic

N21_sout_node[11]_lut_out = N21_cout[10] $ (T2L2 # T2L1);
N21_sout_node[11] = DFFEA(N21_sout_node[11]_lut_out, clock, !sclrp, , , , );

--N21_cout[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

N21_cout[11] = CARRY(N21_cout[10] & (T2L2 # T2L1));


--G1_databint[0] is SubDDS:SubDDSi|AltiMult:Product1i|databint[0]
--operation mode is normal

G1_databint[0]_lut_out = iAMPlifys[0] & !sclrp;
G1_databint[0] = DFFEA(G1_databint[0]_lut_out, clock, , , , , );


--G1_dataaint[8] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[8]
--operation mode is normal

G1_dataaint[8]_lut_out = Q1_q[8] & !sclrp;
G1_dataaint[8] = DFFEA(G1_dataaint[8]_lut_out, clock, , , , , );


--T21L8 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[7]~7
--operation mode is normal

T21L8 = G1_dataaint[8] & G1_databint[7];


--N81_sout_node[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[7]
--operation mode is arithmetic

N81_sout_node[7]_lut_out = T21L7 $ T61L9 $ !N81_cout[6];
N81_sout_node[7] = DFFEA(N81_sout_node[7]_lut_out, clock, !sclrp, , , , );

--N81_cout[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

N81_cout[7] = CARRY(T21L7 & (N81_cout[6] # !T61L9) # !T21L7 & !T61L9 & N81_cout[6]);


--N3_cs_buffer[22] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[22]
--operation mode is arithmetic

N3_cs_buffer[22] = H1L9Q $ N3_cout[21];

--N3_cout[22] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22]
--operation mode is arithmetic

N3_cout[22] = CARRY(H1L9Q & N3_cout[21]);


--N3_cs_buffer[23] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[23]
--operation mode is arithmetic

N3_cs_buffer[23] = H1L01Q $ N3_cout[22];

--N3_cout[23] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23]
--operation mode is arithmetic

N3_cout[23] = CARRY(H1L01Q & N3_cout[22]);


--N3_cs_buffer[24] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[24]
--operation mode is arithmetic

N3_cs_buffer[24] = H1L11Q $ N3_cout[23];

--N3_cout[24] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24]
--operation mode is arithmetic

N3_cout[24] = CARRY(H1L11Q & N3_cout[23]);


--N3_cs_buffer[25] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[25]
--operation mode is arithmetic

N3_cs_buffer[25] = H1L21Q $ N3_cout[24];

--N3_cout[25] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25]
--operation mode is arithmetic

N3_cout[25] = CARRY(H1L21Q & N3_cout[24]);


--N3_cs_buffer[26] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[26]
--operation mode is arithmetic

N3_cs_buffer[26] = H1L31Q $ N3_cout[25];

--N3_cout[26] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26]
--operation mode is arithmetic

N3_cout[26] = CARRY(H1L31Q & N3_cout[25]);


--N3_cs_buffer[27] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[27]
--operation mode is arithmetic

N3_cs_buffer[27] = H1L41Q $ N3_cout[26];

--N3_cout[27] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27]
--operation mode is arithmetic

N3_cout[27] = CARRY(H1L41Q & N3_cout[26]);


--N3_cs_buffer[28] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[28]
--operation mode is arithmetic

N3_cs_buffer[28] = H1L51Q $ N3_cout[27];

--N3_cout[28] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28]
--operation mode is arithmetic

N3_cout[28] = CARRY(H1L51Q & N3_cout[27]);


--N3_cs_buffer[29] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[29]
--operation mode is arithmetic

N3_cs_buffer[29] = H1L61Q $ N3_cout[28];

--N3_cout[29] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29]
--operation mode is arithmetic

N3_cout[29] = CARRY(H1L61Q & N3_cout[28]);


--N3_cs_buffer[30] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[30]
--operation mode is arithmetic

N3_cs_buffer[30] = H1L71Q $ N3_cout[29];

--N3_cout[30] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30]
--operation mode is arithmetic

N3_cout[30] = CARRY(H1L71Q & N3_cout[29]);


--N12_cs_buffer[12] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]
--operation mode is arithmetic

N12_cs_buffer[12] = N51_sout_node[10] $ N21_sout_node[12] $ N12_cout[11];

--N12_cout[12] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[12]
--operation mode is arithmetic

N12_cout[12] = CARRY(N51_sout_node[10] & (N21_sout_node[12] # N12_cout[11]) # !N51_sout_node[10] & N21_sout_node[12] & N12_cout[11]);


--N81_sout_node[6] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[6]
--operation mode is arithmetic

N81_sout_node[6]_lut_out = T61L8 $ T21L6 $ !N81_cout[5];
N81_sout_node[6] = DFFEA(N81_sout_node[6]_lut_out, clock, !sclrp, , , , );

--N81_cout[6] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

N81_cout[6] = CARRY(T61L8 & T21L6 & N81_cout[5] # !T61L8 & (T21L6 # N81_cout[5]));


--N81_sout_node[5] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[5]
--operation mode is arithmetic

N81_sout_node[5]_lut_out = T61L7 $ T21L5 $ !N81_cout[4];
N81_sout_node[5] = DFFEA(N81_sout_node[5]_lut_out, clock, !sclrp, , , , );

--N81_cout[5] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

N81_cout[5] = CARRY(T61L7 & T21L5 & N81_cout[4] # !T61L7 & (T21L5 # N81_cout[4]));


--N12_cs_buffer[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]
--operation mode is arithmetic

N12_cs_buffer[11] = N51_sout_node[9] $ N21_sout_node[12] $ N12_cout[10];

--N12_cout[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

N12_cout[11] = CARRY(N51_sout_node[9] & (N21_sout_node[12] # N12_cout[10]) # !N51_sout_node[9] & N21_sout_node[12] & N12_cout[10]);


--N81_sout_node[4] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[4]
--operation mode is arithmetic

N81_sout_node[4]_lut_out = T61L6 $ T21L4 $ !N81_cout[3];
N81_sout_node[4] = DFFEA(N81_sout_node[4]_lut_out, clock, !sclrp, , , , );

--N81_cout[4] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

N81_cout[4] = CARRY(T61L6 & T21L4 & N81_cout[3] # !T61L6 & (T21L4 # N81_cout[3]));


--N12_cs_buffer[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]
--operation mode is arithmetic

N12_cs_buffer[10] = N51_sout_node[8] $ N21_sout_node[12] $ N12_cout[9];

--N12_cout[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

N12_cout[10] = CARRY(N51_sout_node[8] & (N21_sout_node[12] # N12_cout[9]) # !N51_sout_node[8] & N21_sout_node[12] & N12_cout[9]);


--N81_sout_node[3] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[3]
--operation mode is arithmetic

N81_sout_node[3]_lut_out = T61L5 $ T21L3 $ !N81_cout[2];
N81_sout_node[3] = DFFEA(N81_sout_node[3]_lut_out, clock, !sclrp, , , , );

--N81_cout[3] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

N81_cout[3] = CARRY(T61L5 & T21L3 & N81_cout[2] # !T61L5 & (T21L3 # N81_cout[2]));


--N12_cs_buffer[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]
--operation mode is arithmetic

N12_cs_buffer[9] = N51_sout_node[7] $ N21_sout_node[11] $ N12_cout[8];

--N12_cout[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

N12_cout[9] = CARRY(N51_sout_node[7] & (N21_sout_node[11] # N12_cout[8]) # !N51_sout_node[7] & N21_sout_node[11] & N12_cout[8]);


--N81_sout_node[2] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[2]
--operation mode is arithmetic

N81_sout_node[2]_lut_out = T61L4 $ T21L2 $ !N81_cout[1];
N81_sout_node[2] = DFFEA(N81_sout_node[2]_lut_out, clock, !sclrp, , , , );

--N81_cout[2] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

N81_cout[2] = CARRY(T61L4 & T21L2 & N81_cout[1] # !T61L4 & (T21L2 # N81_cout[1]));


--N12_cs_buffer[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]
--operation mode is arithmetic

N12_cs_buffer[8] = N51_sout_node[6] $ N21_sout_node[10] $ N12_cout[7];

--N12_cout[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

N12_cout[8] = CARRY(N51_sout_node[6] & (N21_sout_node[10] # N12_cout[7]) # !N51_sout_node[6] & N21_sout_node[10] & N12_cout[7]);


--N42_cs_buffer[3] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic